Robust C-element design for soft-error mitigation

Abstract

C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its soft-error tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element.