IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 12 , Issue 10
Showing 1-9 articles out of 9 articles from the selected issue
LETTER
  • Sungho Jeon, Hiroyuki Fujita, Hiroshi Toshiyoshi
    Type: LETTER
    Subject area: Micro- or nano-electromechanical systems
    2015 Volume 12 Issue 10 Pages 20150072
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 08, 2015
    JOURNALS FREE ACCESS
    This paper presents an interactive laser scanning display (LSD) based on a microelectromechanical systems (MEMS) optical scanner that projects full-color images of lateral 720 pixels by two-dimensionally scanning a collimated laser beam. The scanner optics is also designed to function as a laser range finder (LRF) to measure the distance to the screen or an inserted object within arm’s reach of 20 cm to 60 cm. The combination of LSD and LRF constructs an interactive image display that could be remote-controlled by the viewer’s hand gestures.
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  • Yong Chen, Xi Tan, Na Yan, Yibo Fan, Hao Min
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 10 Pages 20150194
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 27, 2015
    JOURNALS FREE ACCESS
    This paper presents a rectifier for passive UHF RFID tags with high power conversion efficiency (PCE) over a wide incident power range under the influence of mismatch between tag antenna and chip, which benefits read and write sensitivities simultaneously. Fabricated with 0.13 µm CMOS technology, the RF frontend adopting this rectifier achieves PCE higher than 25% with incident power from −19.2 dBm to −7.6 dBm.
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  • Peifang Gao, Yuan Bai, Xiurong Ma, Bingxue Chen
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 10 Pages 20150249
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: May 01, 2015
    JOURNALS FREE ACCESS
    A novel pilot pattern selection method is proposed in wireless OFDM systems which can be used for sparse channel estimation. It is that cumulative coherence function is proposed to select optimal pilot patterns. This proposed method can characterize the measurement matrix which is made up of pilot patterns well, it can also remedy the drawbacks that better pilot patterns maybe ignored under the metric of coherence parameter. Simulation results demonstrate that optimal pilot patterns will be obtained by the novel method, and better channel estimation performance can be acquired.
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  • Kyoung Min Lee, Myung Kyoon Yim, Tae Hee Han
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 10 Pages 20150252
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 22, 2015
    JOURNALS FREE ACCESS
    When there is an impending heavy workload under low battery conditions, mobile device such as smartphones can autonomously reset or even shut down to prevent damage caused by sudden voltage drops. Recently, the occurrence probability of sudden voltage drop under low battery conditions has increased with the use of high-performance 64-bit CPU cores, which adversely affects the user experiences. To overcome this problem, we propose a cost-effective sudden-voltage-drop protection (SVDP) technique to minimize unstable states, thus enhancing customer satisfaction. Programmable low-battery-state-aware logic for sudden voltage drop detection and performance tuning to maintain system stability via clock frequency control is incorporated in power management integrated circuit (PMIC) and application processor (AP). Experimental results show that the proposed technique significantly reduces the failure rate due to sudden voltage drops under low battery conditions.
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  • I-Chyn Wey, Bing-Chen Wu, Chien-Chang Peng, Cihun-Siyong Alex Gong, Ch ...
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 10 Pages 20150268
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 22, 2015
    JOURNALS FREE ACCESS
    C-element is a widely used component in soft-error tolerant designs to construct a robust soft-tolerant mechanism; however, C-element itself is not a robust device. In this paper, we proposed a robust C-element design by employing two transistors operating in saturation region parallel connected with C-element upper pMOS and lower nMOS to enhance its soft-error tolerance. By utilizing the proposed C-element in the prior-art isolated latch designs, the maximum soft error tolerance can be improved by 25.87% as compared with conventional C-element.
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  • Sukanta Roy, Harikrishnan Ramiah, Ahmed Wasif Reza
    Type: LETTER
    Subject area: Micro- or nano-electromechanical systems
    2015 Volume 12 Issue 10 Pages 20150272
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: May 12, 2015
    JOURNALS FREE ACCESS
    A novel sustaining amplifier is designed and characterized for a Si-based MEMS resonator, in implementing a reference oscillator in 180 nm CMOS process. A two port electrical model of the MEMS resonator is used to compute the insertion loss (−76 dB) and phase shift (95°). Total open loop transimpedance gain is achieved as 122 dBΩ with −70° phase shift, at the resonant frequency of 17.22 MHz. This amount of gain is investigated as capable to sustain MEMS resonator’s oscillation, in the realization of a cost effective, miniaturized and low power CMOS reference oscillator which oversees on application in clock generation.
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  • Amir Almslmany, Qunsheng Cao, Caiyun Wang
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 10 Pages 20150291
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 27, 2015
    JOURNALS FREE ACCESS
    Deception jammer is the most effective technique for spoofing a radar system. In this paper a new model for airborne self-protection jammer was proposed, this model provides a countering technique to the ground radars. It is used for generating a deceptive jamming signal using digital radio frequency memory (DRFM) based on sub-Nyquist sampling, it shows that under sampling with lower sampling rates will be useful in generating a multiple deceptive false target signals with a better resolution, it has greatly reduced the demands on sampling rate, processing time, and power transmitted.
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  • Hyun-Wook Kang, Hyeok-Ki Hong, Sanghoon Park, Ki-Jin Kim, Kwang-Ho Ahn ...
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 10 Pages 20150302
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 22, 2015
    JOURNALS FREE ACCESS
    A ternary-level thermometer capacitive digital-to-analog converter (C-DAC) switching scheme is proposed for flash-assisted successive-approximation register (FA-SAR) analog-to-digital converters (ADCs). By minimizing the capacitor reference switching operations of the C-DAC with the help of thermometer codes readily available from the assistant flash ADC, integral nonlinearity (INL) and differential nonlinearity (DNL), as well as C-DAC switching energy, are significantly improved from conventional switching schemes, which in turn makes near thermal-noise-limited capacitor designs feasible without complex capacitor weight calibrations.
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  • Jizeng Wei, Yisong Chang, Bingchao Li, Wei Guo, Jizhou Sun
    Type: LETTER
    Subject area: Storage technology
    2015 Volume 12 Issue 10 Pages 20150314
    Published: 2015
    Released: May 25, 2015
    [Advance publication] Released: April 27, 2015
    JOURNALS FREE ACCESS
    The traditional post-TnL vertex cache (abbr. ‘post-VC’) in embedded GPUs (EGPUs) with only one vertex or unified shader does not fit to multi-shader EGPUs for two reasons. As multiple shaders run in parallelism, (a) the out-of-order vertex processing may raise the post-VC inconsistency that leads to cache the error data, and (b) it is very hard to detect in time which vertices are saved in the post-VC in the stage of vertex fetching, resulting in the low performance. In this paper, we propose a modified post-VC including a decoupling cache and a vertex batch in-order commit controller, which can guarantee that the data SRAM and index tag can be updated in-order according to the same replacement policy in the different stages of vertex processing. The function of the proposed post-VC is verified on a FPGA-based platform. Experimental results show that it increases the performance by an average of 172% and 80.6% compared to the EGPU without/with the traditional post-VC respectively at a little expense.
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