Efficient systolic modular multiplier/squarer for fast exponentiation over GF(2^m)

抄録

Using the concept of common components, this letter shows that field multiplication and squaring over GF(2^m) can be efficiently combined, with little hardware overhead. The analysis results show that about 39.23% area-time (AT) complexity is improved when we employ the combined systolic multiplier/squarer instead of implementing the multiplier and the squarer separately in the least significant bit (LSB)-first exponentiation. The proposed architecture features regularity, unidirectional data flow, and local interconnection, and thus is well suited to VLSI implementation.