IEICE Electronics Express
Online ISSN : 1349-2543
On-chip interconnect boosting technique by using of 10-nm double gate-all-around (DGAA) transistor
Jaemin LeeMyunghwan RyuYoungmin Kim
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2015 Volume 12 Issue 12 Pages 20150321


Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore’s law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAA-based designs.

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© 2015 by The Institute of Electronics, Information and Communication Engineers
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