A novel motion compensation method, which is based on the approximate total least squares (ATLS) algorithm, for wide-beamwidth SAR systems is proposed in this paper. The method is suitable for situations where both the estimated phase errors and the geometry of SAR imagery are corrupted by noise. The precondition that the noise belongs to a certain distribution model is not necessary, which makes it more robust for many kinds of scene content. As a consequence, higher accuracy of the estimated motion error and better focused image are achieved. Simulated and real data imaging demonstrate the validity of the proposed method.

View full abstract

A wide-range and fast-locking all digital successive approximation register-controlled delay-locked loop (SARDLL) is presented for dynamic voltage/frequency scaling (DVFS) system-on-chips (SoCs). The proposed SARDLL eliminates the harmonic lock problem and zero-delay trap problem by using the improved resettable digitally controlled delay line (DCDL) and shortens the lock time by adopting the 2-b successive-approximation-register (SAR) algorithm. The proposed 6-bit SARDLL is designed using the TSMC 65 nm CMOS low power cell library. The layout’s active area is 91 µm × 91 µm. The post-layout simulation results show that the proposed SARDLL can operate from 250 MHz to 2 GHz. Its lock time is constant 9 cycles of the input clock. The power consumption is estimated to be 0.72 mW at 1.2 V supply voltage and 2-GHz clock frequency.

View full abstract

Increasing short channel effects (SCEs) hinder further technology downscaling of CMOS transistors. Beyond the 10-nm technology node, the gate-all-around (GAA) FET is considered a promising solution for continuing Moore’s law. In this study, we introduce a novel structure for speeding up the interconnect propagation using 10-nm channel length double gate-all around (DGAA) transistors. We propose a boosting structure that can significantly improve the performance of circuits by controlling the two gates of the DGAA independently. The proposed structure demonstrates that the propagation delay can be reduced by up to 30% for short interconnects and 47% for long interconnects. In high-speed, low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between power consumption and performance, which will play an important role in application-specific integration circuits in future GAA-based designs.

View full abstract

This paper proposes a high-image-rejection wireless-receiver architecture with a 3-phase active RC complex filter. The double conversion receiver, in cooperation with RF filter, rejects all image signals. In particular, the double conversion corrects the gain and phase mismatches of the adjacent image, and the image-rejection ratio of the adjacent image depends only on RC mismatches in the complex filter. Thus, the total image-rejection ratio of more than 60 dB can be expected for all the image signals.

View full abstract

In view of the high energy consumption and latency problem due to multi-hop wired links between distant cores of traditional large-scale Network-on-Chip, a virtual torus-based adaptive wireless NoC architecture has been proposed when analyzing the existing several wireless NoC architectures. By not only adopting the automatic detection and dynamic bandwidth allocation mechanism to hot wireless link based on the sensing parameter for improved congestion measurement, but also designing the Dynamic Allocation Control Circuit Module (DACCM) for transmitter, the intra-chip topology and link bandwidth could be adaptively adjusted as different traffic patterns. Experimental results show that the proposed architecture has more significant latency improvement and energy saving under different traffic patterns or real application such benchmark as FFT.

View full abstract

A symmetric tunnel field-effect transistor (S-TFET) was recently proposed as an alternative device to address power density issues, featuring steep switching characteristic and bi-directional current flow with its symmetric structure. Because 193-nm immersion lithography is paired up with double or multiple patterning techniques for further enhancement of patterning resolution, the effect of double-patterning and double-etching (2P2E)-induced gate line-edge roughness (LER) [versus single-patterning and single-etching (1P1E)] on the S-TFET is investigated with various device design parameters. Finally, an investigation is conducted on the physical reasons which give rise to the difference in the LER parameters for 2P2E and 1P1E technique.

View full abstract

Diameter and average distance are two important metrics in topology selection for on-chip networks. In order to lower down them in Mesh, DMesh is proposed by introducing diagonal links. Compared to Mesh, the port number in routers of DMesh almost doubles, thus high-radix routers are required. The ever increasing pin bandwidth enables design of high-radix routers to improve performance of the overall network. However, the original algorithm DXY always prefers to use the crossing links, and does not make efficient use of physical channels. Though quasi-minimal routing algorithm provides some adaptivity, it limits packets routing in the rectangular defined by source and destination nodes. In this paper, we present a novel deadlock-free and livelock-free routing algorithm for DMesh, and it provides much more flexibility for packets in order to make better use of different links. Simulation results validate the effectiveness of the novel routing scheme as compared to the existed algorithms.

View full abstract

This letter presents a multi-cell battery pack monitoring chip for electric vehicles (EVs). A multiplexer based on p- and n-type lateral double-diffused MOS (LDMOS) transistors is proposed to select the battery voltage in a battery pack with up to 12 series-connected battery cells. Measuring of the cell voltages is realized by a 12-bit incremental ΣΔ analog-to-digital converter (ADC) with offset cancellation. Fabricated in a 0.35-µm Bipolar-CMOS-DMOS (BCD) technology, measurement results show that an absolute conversion error of less than 3 mV is obtained. The conversion time for each cell is less than 600 µs under a 1-MHz clock signal generated by an internal oscillator. The chip area is 4 × 3.8 mm² and the current consumption is 510 µA in measuring mode, resulting in a operation power loss of 25.5 mW under a 50-V power supply.

View full abstract

In this paper, we propose the parallel architecture for high speed calculations of SHA-1, a widely used cryptographic hash function. Parallel SHA-1 consists of a number of base modules which process the message digest in parallel manner. The base module uses state of art SHA-1 acceleration techniques: loop unfolding, pre-processing, and pipelining. We achieved the performance improvement of 5.8% over the pipeline architecture that is known to have nearly achieved the theoretical performance limit. We implemented our system on the Xilinx Virtex-6 FPGA and verified the operations by interfacing it with MicroBlaze soft processor core.

View full abstract

This paper has presented a non-contact vibration sensor based on fiber Bragg grating (FBG) sensing, and applied to measure vibration of turbine rotor dynamic balance platform. The principle of the sensor has been introduced; it’s based on magnetic coupling principle and the FBG sensing to obtain the vibration. The sensors calibration experiments show that: sensitivity of 1^st sensor in range of 3.00–3.80 mm is −449.83 pm/mm, linearity is 5.19%; sensitivity of 2^nd sensor in range of 4.00–5.00 mm is −430.95 pm/mm, linearity is 3.31%. In addition, turbine rotor dynamic vibration detection system based on eddy current displacement sensor and non-contact FBG vibration sensor have set; and contrast analysis of experiments data shows that: the vibration signal analysis of non-contact FBG vibration sensor is basically the same as the result of eddy current displacement sensor. It verified that the sensor can be used for non-contact measurement of turbine rotor dynamic balance vibration.

View full abstract

Through silicon via (TSV) is a key technology in 3-D integrated circuits (3-D ICs). At the junction of TSV and pad, an extra loss produced by the discontinuous structure is inevitable in microwave circuit, and it can not be ignored. A compensation structure which can compensate the loss from step change in radius is proposed in this paper. The conventional structure and compensation structure are simulated by High Frequency Structure Simulator (HFSS). Simulation result shows that the proposed compensation structure can effectively reduce the return loss within the whole frequency range, and the compensation of insertion loss is more obvious at higher frequency. A series of top layer compensation structures with different diameter ratios are simulated. The simulation result shows that the larger the diameter ratio, the more obvious the compensation is. As the analysis based on the impedance model of TSV correlates well with the simulations, the proposed compensation structure is a worthwhile guideline for the design of 3-D ICs.

View full abstract

In this study, the signal paths in intrabody communication channels are discussed by evaluating the electric fluxes between conductors and the earth ground. This study is based on the equivalent circuit model of which parameters are obtained via an electrostatic analysis. The obtained results clarified the electric flux flows in the communication channels, and they quantitatively support the previous study reported by one of the authors.

View full abstract

We conducted an experiment to demonstrate the generation of multiwavelength by incorporating fibre Bragg gratings (FBGs) and photonic crystal fibre (PCF) which has zero dispersion of 1040 nm and 1550 nm in erbium doped fibre ring laser (EDFRL). The multiwavelength was generated at gain bandwidth EDFRL setup. The results showed a good agreement of less than 0.03% of peaks wavelength generation based on both experimental set-up. The setup also share good repeatability of peaks wavelength generation of 0.01 nm and power deviation of 0.15 dBm. Nevertheless, experimental set-up with PCF of ZDW at 1550 has generated multi wavelength phenomenon by 30% effectively compared to PCF with ZDW at 1040 nm by 30% effectively. The results produced an impactful finding whereby the multiwavelength were clearly observed.

View full abstract

The measurement of static test parameters for an analog-to-digital converter (ADC) requires a large volume of test data, especially for a high-resolution ADC. This paper proposes a reduced-code test method for pipelined ADCs that does not compromise test accuracy. The proposed method calculates fault information at each stage by using sub-histograms. The simulation results based on 12-bit pipelined ADCs show a maximum integral nonlinearity error of 0.590 LSB with only 3.92% of the codes required for the conventional histogram-based method.

View full abstract

A compact ultra-wideband (UWB) power divider with favorable selectivity is proposed. A transversal filtering transformer consisting of two different centrally loaded resonators with common feeding lines is introduced at input port to obtain good in-band response and high out-of-band rejection. Simple and rapid design procedure is adopted to find the key parameters. A prototype power divider is designed and fabricated to validate the predicted features. Measured results show that the power divider is featured by sharp roll-off skirts and large stopband attenuation.

View full abstract

This letter proposes a novel on-chip step-dimmer using an analog dimming method for a high PF AC-powered LED driver. The full AC LED driver can achieve a very high PF and a low THD by using a self-adaptive power processing circuit while delivering a best-in-class dimming performance with the proposed step-dimmer. Under the control of the dimming signal, the dimming voltage is step-adjusted from 1.0 V to 2.5 V, the average LED current can be changed from 40% to 100% of the nominal LED current value. To verify the feasibility of the proposed scheme, an 8-string 4.4 W AC-powered LED driver with the proposed step-dimmer was designed and simulated using a 0.35 um-700 V BCD Magnachip process. The gained results verify that the proposed step-dimmer can maintain a high performance of the AC LED driver under different dimming modes with a PF and a THD around 0.998 and 6%, respectively.

View full abstract