A low-distortion ΣΔ capacitive microaccelerometer with self-test circuit

Abstract

A low-distortion ΣΔ interface with self-test circuit is proposed for a closed-loop capacitive microaccelerometer. A fully feedforward architecture is used to reduce integrator output swing and decrease distortions of the ΣΔ interface circuit, resulting in a reduction of power dissipation. A self-test circuit is proposed to measure the distortions of the microaccelerometer without using a vibration table. A fourth-order closed-loop capacitive microaccelerometer is proposed to verify the effectiveness of the technique. The interface circuit is designed and the chip is fabricated using a standard 0.35 µm CMOS process. The capacitive microaccelerometer consumes 10 mW from a 5 V supply with a sampling frequency of 250 kHz. It achieves a noise floor of 9 µg/Hz^1/2, and the self-test measurement results show that the resulting HD2 and HD3 of the microaccelerometerare −92.28 dB and −99.27 dB, respectively.