This paper presents experimental analysis of chaotic dynamics in a variable memristor-based Chua’s Circuit. The equivalent memristor used as a nonlinear resistor of the Chua’s circuit comprises operational amplifiers, multipliers, several passive elements, and variable resistor for its hysteresis loop control. Chaotic dynamics such as attractors and bifurcation were examined using a control resistor of the memristor as a variable resistor. Moreover, we showed the subtle dependence on the hysteresis loop of the memristor in Chua’s circuit. The circuit was experimentally implemented using an electronic circuit and measurements were noted. The implemented circuit showed intermittent chaotic dynamics from 4.3 kΩ to 16.1 kΩ in control resistor of the memristor. The simulated and measured results verified that the chaotic dynamics of the proposed circuit could be created and controlled using a variable memristor.
This paper discusses impacts of flexible Vth control, low process variability, and steep SS with small on-current of new structure devices on ultra-low voltage circuits. Our simulation results based on PTM 22 nm model clarify applicability of ultra-low voltage operation to a nominal speed common SoC designs by an introduction of Vth control as well as low power sensor nodes. We also reveal requirement of process variability suppression for high energy efficiency with steep SS transistors, and utilization of small on-current steep SS transistors to low power and low speed applications. Our qualitative discussion well explains these experiment results.
A feedback current output digital to analog converter (DAC) is proposed to improve the linearity of frequency and reduce the power consumption in this synthesized PLL. All circuit blocks are implemented with standard cells from digital library and place-and-routed automatically without any manual routing. The proposed PLL has been fabricated in a 28 nm fully depleted silicon on insulator (FDSOI) technology. The measurement results show that this synthesized injection-locked PLL consumes 1.4 mW from 1 V supply while achieving a figure of merit (FoM) of −235.0 dB with 1.5 ps RMS jitter at 1.6 GHz. This chip occupies only 64 µm × 64 µm layout area with the advanced 28 nm FDSOI process. To the best knowledge of the authors, the PLL presented in this paper achieves the smallest area to date.
An improved figure-of-merit (FoM) equation is proposed for op-amp evaluation. This equation has a modification factor to include the effect of the phase margin, which is not considered in a conventional FoM equation. Simulation results confirm that the proposed FoM equation drastically suppresses the effect of load capacitance variations. By using the proposed FoM equation, evaluations of op-amps become more reasonable as compared with the comparisons using the conventional FoM equation.
A low-distortion ΣΔ interface with self-test circuit is proposed for a closed-loop capacitive microaccelerometer. A fully feedforward architecture is used to reduce integrator output swing and decrease distortions of the ΣΔ interface circuit, resulting in a reduction of power dissipation. A self-test circuit is proposed to measure the distortions of the microaccelerometer without using a vibration table. A fourth-order closed-loop capacitive microaccelerometer is proposed to verify the effectiveness of the technique. The interface circuit is designed and the chip is fabricated using a standard 0.35 µm CMOS process. The capacitive microaccelerometer consumes 10 mW from a 5 V supply with a sampling frequency of 250 kHz. It achieves a noise floor of 9 µg/Hz1/2, and the self-test measurement results show that the resulting HD2 and HD3 of the microaccelerometerare −92.28 dB and −99.27 dB, respectively.
We present an on-chip measurement technique to characterize the jitter tolerance of a clock and data recovery (CDR) circuit. The proposed jitter modulation scheme incorporates a modulated-charge-pump and a pulse generation circuits to apply a periodic triangular form voltage directly to the control voltage of CDR circuit. This jitter frequency generation scheme independent from the VCO in the CDR allows a wide and linear control of jitter. The modulated jitter amplitude range was 0.05–2 UIpp at 10 MHz, and the jitter frequency range was 100 KHz–20 MHz. The circuit was fabricated in 65 nm CMOS, and the jitter tolerance was successfully measured at 5 Gbps with a 27-1 PRBS pattern. The accuracy was within 10% error from the external BER equipment measurement result. The whole CDR circuit consumes 29.9 mW at a supply voltage of 1.2 V.
For realizing compact breath sensing device, we have proposed a silica high-mesa waveguide for the gas-cell (breath detection part) because of its low propagation loss. It is, however, still difficult to make breath-sensing due to its total insertion loss because the required length of the waveguide reaches very long of approximately several 10 cm–1 m for the small portion of gas, and thus gas-sensing has not been achieved so far. To compensate the insertion loss, we utilize “amplified” CRDS (cavity ring down spectroscopy) technique to realize gas-sensing in this paper. As a result, we could successfully confirm the gas-sensing of CO2 with using the waveguide gas-cell for the first time.