抄録
With scaling technology node, soft error has dominated in the integrated circuit failure. To tradeoff the design cost and reliability, efficient reliability analysis methods are required to select the appropriate reliable schemes. In this paper, we propose a multi-level Probabilistic Graphical Models (PGM) based method for the soft error analysis of data Cache structure. The proposed method includes two points: 1) Exacting the error masking dependencies from the ALU instruction execution procedure, and calculating the first-level masking rate between ALU and register file; 2) Drawing the error spreading dependencies graph from the load and store instruction processing, and computing the higher-level masking rate between ALU and Data Cache. The simulation results of SPEC2K demonstrate that, compared with the existing methods, the proposed method achieve up to 16.19% accuracy improvement and 52.72× speedup.
