A low jitter phase-locked loop based on self-biased techniques

抄録

A low jitter phase-locked loop (PLL) based on self-biased techniques was designed. The PLL achieves process independent and low input tracking jitter. A novel cascode charge pump (CP) is realized to improve the current matching so as to reduce the jitter of the system. A capacitor is employed in the second CP to make third order PLL. The PLL is fabricated in SMIC 0.13 µm CMOS process, which achieves a very wide tuning range from 625 MHz to 1.5 GHz. And the phase noise of the VCO at 1 MHz offset from the 1.25 GHz only has −94.66 dBc/Hz. The measured RMS jitter and peak-to-peak jitter at 1.25 GHz only have 3.53 ps and 21.19 ps.