IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
High speed DC-DC dead time architecture
Jani Järvenhaara, Hans Herzog, Sami Sipilä, Jing Tian, Igor M. Filanovsky, Nikolay T. Tchamov
Author information
Keywords: DC-DC converters, cascode, dead time auto-generation
JOURNAL FREE ACCESS

2015 Volume 12 Issue 19 Pages 20150662

Browse “Advance online publication” version
Details
Download PDF (472K)
Download citation RIS

(compatible with EndNote, Reference Manager, ProCite, RefWorks)

BIB TEX

(compatible with BibDesk, LaTeX)

Text
How to download citation
Contact us
Abstract
A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240 MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.
Content from these authors
© 2015 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article
Favorites & Alerts

Recently viewed articles
Share this page
feedback
 Top