High speed DC-DC dead time architecture

Jani Järvenhaara; Hans Herzog; Sami Sipilä; Jing Tian; Igor M. Filanovsky; Nikolay T. Tchamov

doi:10.1587/elex.12.20150662

LETTER

High speed DC-DC dead time architecture

Jani Järvenhaara, Hans Herzog, Sami Sipilä, Jing Tian, Igor M. Filanovsky, Nikolay T. Tchamov

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Keywords: DC-DC converters, cascode, dead time auto-generation

JOURNAL FREE ACCESS

2015 Volume 12 Issue 19 Pages 20150662

DOI https://doi.org/10.1587/elex.12.20150662

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Abstract

A novel and simple solution for adjusting dead time in high speed DC-DC converters is proposed. The usual dead time adjustment of DC-DC converters through feedback control has limited speed. For the high speed converters extra circuitry and delays in the feedback should be minimized. A 240 MHz DC-DC converter with the presented dead time circuit is designed on low-voltage fast CMOS process.

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