Single event transient propagation in dynamic complementary metal oxide semiconductor cascade circuits

Abstract

In this paper, the propagation of SET in dynamic CMOS cascade circuits is studied. Based on the domino logic buffer chain and the static inverter chain, the SET propagation was simulated by large amount of random singe event current transient injecting in spice simulation. It can be found that the propagation probability of SET in the domino logic buffer chain is 15.7% of that in the static inverter chain. With the simulation results, it can be deduced that in other logic gate cascade structures, the propagation probability of SET in dynamic CMOS cascade circuits is reduced significantly compared with that in the static circuits.