A 14-bit 100 MS/s SHA-less pipelined ADC with 89 dB SFDR and 74.5 dB SNR

Abstract

In this paper, a 14-bit 100 MS/s pipelined Analog-to-Digital Converter (ADC) in 0.18 µm CMOS process with a SHA-less frontend is demonstrated. The methods of clock adjustment and voltage reference separation are proposed to speed up the settling of residue amplifier. Meanwhile, an effective digital background calibration mechanism is employed in the first two stages to correct both capacitor mismatches and linear gain error of residue amplifier. After calibration, the presented ADC achieves an spurious-free dynamic range (SFDR) of 89 dB, a signal-to-noise ratio (SNR) of 74.5 dB and a signal-to-noise and distortion ratio (SNDR) of 74.2 dB with a 30.2 MHz input signal, while keeping over 71.6 dB SNR and 70.2 dB SFDR with input signals up to 200 MHz. The chip consumes 440 mW from a 1.8 V supply and occupies an area of 4 × 2.6 mm².