抄録
This paper presents a receiver design with the on-off keying (OOK) modulation at 315 MHz frequency. In this design, we propose a new architecture for the receiver to achieve low complexity with a solution to reduce total power consumption significantly. The operation of the proposed architecture is verified using available RF front-end circuits and a field-programmable-gate-array (FPGA) device. Circuit of the receiver is designed by using SPICE models of 65 nm Silicon On Thin Buried Oxide (SOTB) CMOS technology. By simulation, the receiver achieves −76 dBm sensitivity, consumes 27.6 µW from 1 V supply voltage with data rate up to 200 Kbps.
