Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol. 12 (2015) No. 5 pp. 20150102]

Chunyu Peng; Youwu Tao; Wenjuan Lu; Zhengping Li; Xinchun Ji; Jinlong Yan; Junning Chen

doi:10.1587/elex.12.20158001

IEICE Electronics Express

Online ISSN : 1349-2543
ISSN-L : 1349-2543

ERRATA

Erratum: A novel cascade control replica-bitline delay technique for reducing timing process-variation of SRAM sense amplifier [IEICE Electronics Express Vol. 12 (2015) No. 5 pp. 20150102]

Chunyu Peng, Youwu Tao, Wenjuan Lu, Zhengping Li, Xinchun Ji, Jinlong Yan, Junning Chen

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2015 Volume 12 Issue 7 Pages 20158001

DOI https://doi.org/10.1587/elex.12.20158001

IEICE Electron. Express : Vol. 12 (2015) No. 5 pp.20150102-20150102

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