IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 12 , Issue 7
Showing 1-22 articles out of 22 articles from the selected issue
REVIEW PAPER
  • Mitsumasa Koyanagi
    Type: REVIEW PAPER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20152001
    Published: 2015
    Released: April 10, 2015
    JOURNALS FREE ACCESS
    3D integration technology is the key for future LSIs with high-performance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.
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  • Takayuki Ohba, Youngsuk Kim, Yoriko Mizushima, Nobuhide Maeda, Koji Fu ...
    Type: REVIEW PAPER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20152002
    Published: 2015
    Released: April 10, 2015
    JOURNALS FREE ACCESS
    The prospects of three-dimensional (3D) integration for Terabyte large scale integration using bumpless interconnects with low-aspect-ratio TSVs and ultra-thinning are discussed. Bumpless (no bump) interconnects between wafers are a second-generation alternative to the use of micro-bumps for Wafer-on-Wafer (WOW) technology. Ultra-thinning of wafers down to 4 µm provides the advantage of a small form factor, not only in terms of the total volume of 3D ICs, but also the aspect ratio of Through-Silicon-Vias (TSVs). Our bumpless interconnects technology is classified into Via-Last, which is performed from the front side after thinning, and stacking Back-to-Front, in which any number of thinned 300 mm wafers and/or heterogeneous dies can be integrated. From an economic point of view, in many situations WOW is the leading 3D process because stacking at the wafer level drastically increases the processing throughput, and using multi-level bumpless interconnects, with individual wiring die-to-die, provides an appropriate yield that is equivalent to or greater than that achievable with 2D processes when scaling down to 22 nm nodes and beyond.
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LETTER
  • Hao Wang, Zhangming Zhu
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20141202
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    A novel switching scheme for low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive approximation register (SAR) analogue to-digital converters (ADCs) is presented which requires only 2 references, VREF and ground. With the monotonic capacitor switching procedure and C-2C dummy capacitor, the proposed switching scheme achieves 90.61% less switching energy, 74.7% less area and 41.18% less number of switches compared to conventional architecture, which results in an energy-efficient and switch-fewest switching scheme. Behavioral simulation results prove the effectiveness of the proposed switching scheme.
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  • Ailing Li, Yan Han, Jun Sun
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20141220
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 19, 2015
    JOURNALS FREE ACCESS
    This paper presents an innovative method to decrease the discreteness of minimum tripping current for type A residual current operated circuit breakers (RCCBs). Different but continuous time intervals’ detection method is proposed to identify the residual current’s type and judge whether its root mean square (RMS) value has exceeded the rated value in one cycle. That is, after the timer is started, 0–3 ms ±135° leakage current is detected, 3–7 ms ±90° is detected, 7–12 ms ±0° is detected, 3–7 ms and 12–16 ms type AC is detected. What’s more, the method is fabricated in a mixed-signal 0.5 µm CMOS process, and test results show that the type A RCCB’s tripping current variation is decreased to 2.8 mA, which greatly improves the chip’s reliability and anti-interference ability.
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  • Tong Ling, Huajun Fang, Xiao Zhao, Jun Xu
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20141226
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    This paper introduces a method named Chopping-Out-Of-band (COOB), which can suppress ripple in chopper amplifiers. By choosing a suitable chopping frequency (fchop) located in GBW < fchop < NLBW (No-Load Bandwidth), the ripple will be suppressed rather than amplified and the effect can be improve further by an extra filter. The COOB technique was employed in instrumentation amplifiers as examples and the extra filter was designed to passive filter. These chopper amplifiers were simulated on UMC 0.18 um technology with the help of Cadence SpectreRF. Simulation results showed that the ripple was suppressed by −93.4 dB in Power Spectral Density (PSD) analysis without additional power consumption.
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  • Chenming Zhong, Bin Luo, Feng Ning, Wan Liu
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150016
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    For wireless power transferred (WPT) system with multi-receiver, the cross coupling effect between non-adjacent coils may seriously impact the performance of the system, decreasing the transferred power and the efficiency. In this paper, a theoretical analysis on the transferred power and the efficiency of two kinds of WPT system models with two-receiver is proposed via circuit theory. Furthermore, a reactance compensatory method is proposed to eliminate the adverse effect brought about by cross coupling, as well as a performance evaluated method introduced for comparing the transferred power and the efficiency before and after compensation. Numerical simulations and experimental results show the transferred power and the performance score are increased remarkably after compensationand it verifies the feasibility of this compensatory method.
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  • Kyosuke Muramatsu, Hideaki Asakura, Keijiro Suzuki, Ken Tanizawa, Mune ...
    Type: LETTER
    Subject area: Optoelectronics, Lasers and quantum electronics, Ultrafast optics, Silicon photonics, Planar lightwave circuits
    2015 Volume 12 Issue 7 Pages 20150019
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    The phase errors in 100-GHz spacing, 8-ch, Si-wire arrayed-waveguide gratings (AWG) fabricated by ArF-immersion photolithography were measured by the frequency-domain interference method. To our knowledge, this is the first time phase error measurements in a Si-wire AWG have been performed. By comparing the reconstructed transmission spectrum to the directly measured spectrum, the accuracy of this phase error measurement was confirmed. The average phase error in the AWGs on 6 chips was 0.27π radian, and this value is equivalent to a fluctuation in the effective refractive index of 1.1 × 10−4.
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  • Zhanghong Tang, Qun Wang, Xinxin Xu, Hong Xiao, Meiwu Shi
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150037
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    In this paper, the absorbing effectiveness of spherical particle absorber made of cheap Fe-rich hollow cenosphere fly-ash is analyzed. The effects of the diameter of spheres, the number of layer and the stack modes of sphere particle on the absorbing effectiveness were explored. Based on the results, a three-layer structure with mixed sizes of spheres was designed, constructed and tested. Obtained results show that this structure has a maximal reflection loss of 9 dB and the bandwidth being higher than 5 dB is more than 17 GHz. When applying the permittivity of Fe-rich hollow cenosphere fly-ash, and the thickness of absorber is 6.5 cm, the maximal reflection loss is 23 dB and the bandwidth being lower than −10 dB is more than 14 GHz, which covers the C, X and Ku bands. The experimental test proved that the three-layer structure absorber has good absorbing effectiveness.
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  • Lin Zhou, Huotao Gao, Huajun Zhang, Hao Li, Huaqiao Zhao, Fan Wang
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150057
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    In this paper, the design and implementation of a smart antenna system for ultra high frequency (UHF) vehicle-mounted communication is proposed. The project adopts the improved multiple signal classification (MUSIC) algorithm which realized in field programmable gate array (FPGA), and implements robust superdirective beamforming algorithm based on digital signal processor (DSP). They contribute to achieving super-resolution target direction-finding and gaining output beam signals. This solution has greatly improved the signal interference noise ratio (SINR) and the signal's intensity in communication. The experimental results indicate that the system works smoothly with a rapid response and a strong stability, and satisfies the demand of engineering application.
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  • Jintao Zheng, Ning Wu, Gaizhen Yan, Fen Ge, Lei Zhou
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20150065
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    Taking advantage of Three Dimension (3D) Integrated Circuit (IC) technology, 3D Network-on-Chip (NoC) is becoming a promising architecture of high-performance System-on-Chip (SoC). To model 3D NoC and to evaluate the performance fast and accurately, the simulation method is therefore critical issue. Compared to software simulation, Field Programmable Gate Array (FPGA) based simulation can offer a high speed validation process with a higher accuracy. But there still exist some difficulties such as partition, scalability and so on. This paper proposed a novel multi-FPGA simulation platform, RcEF3Ns (Reconfigurable Simulation on multi-FPGA for 3D NoCs), based on Xilinx Virtex-6 FPGAs. The design method of RcEF3Ns employs a single FPGA to manage vertical transaction independently, supporting bus and network communication mechanism. All the parameters can be dynamically reconfigured on-chip to model 3D NoC architecture without re-synthesizing. The experiments show RcEF3Ns’ speedups over 10 times without sacrificing accuracy when compared to other hardware based platform.
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  • Xiaolong Ma, Huaxiang Yin, Peizhen Hong
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150094
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    For the first time, a Gate-All-Around (GAA) Silicon Nanowire Transistor (SNWT) with one special nanowire channel-last (NCL) process technology on silicon (Si) substrate is reported. Different from the traditional approach that the nanowire channels are formed and released at the initial steps of the process flow, the NCL process features the release of nanowire channels in high-k/metal gate-last process during the integration of conventional bulk-Si FinFET. It provides a stable way for the introduction of nanowire transistors in the FinFETs process for mass productions. The fabricated n-type transistors with the effective nanowire diameter (DNW) of 12 nm∼17 nm and the gate length of 100 nm demonstrated excellent subthreshold characteristics (subthreshold swing = 64 mV/V and drain induced barrier lowering = 24 mV/V). Meanwhile, it’s found that the H2 baking process as well as the optimized interface gate oxidation on NW channels greatly improved the device’s SS and off-current parameters.
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  • Il Pyo Roh, Yun Heub Song, Jin Dong Song
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150098
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    We present a novel junction device with bidirectional current flow for switching devices in a high density spin torque transfer magnetic random access memory (STT-MRAM). In this structure, an N+ type strained SiGe material is adopted as a conduction layer to generate higher electron mobility and a flatter doping profile. A SiGe/Si/SiGe heterojunction structure is also used to obtain a better Ion/Ioff ratio due to a steeper junction profile. It is confirmed by 3D simulation that this structure provides higher current drivability and Ion/Ioff ratio. After the simulation, a junction device with N+ Si0.8Ge0.2/P Si/N+ Si0.8Ge0.2 and an area of 4 × 4 um2 is fabricated and evaluated for bidirectional current flow. From the results obtained, we propose that this bidirectional switching device with a heterojunction structure is a promising candidate for a high density STT-MRAM.
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  • Zhiping Wu, Ning Wu, Lei Zhou, Fen Ge
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20150101
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    Recently, 3D NOC is proposed as an efficient architecture to optimize system performance. However, its die-stacking architecture further results in severe heat and traffic congestion problem. In the view of that, a new Adaptive Thermal and Traffic Balanced ZXY Routing algorithm (ATTBR) is proposed to solve the problems. Experiments has shown that, in the 4 × 4 × 4 3D Mesh, ATTBR has a better throughput and average delay performance achieves 34.67% and 14.85% increment in Temperature-Traffic Balance Product which indicates thermal and traffic balance performance, compared to Regional avoidance routing algorithm and Vertically Downward Routing algorithm.
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  • Jun Dong, Tao Yang, Yu Liu, Yihong Zhou, Haiyan Jin
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150117
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    In this work, a broadband stripline-to-rectangular waveguide transition is presented. It uses a rectangular-shaped probe to couple the energy from rectangular waveguide to stripline. The two ground planes of the stripline are extended for field matching of the transition. A back-to-back transition prototype at Ka-band is designed, fabricated and measured. The measured results show that the transition has less than 1.2 dB insertion loss and better than 15 dB return loss over the frequency range from 26.5 to 40 GHz. The 15 dB fractional bandwidth is increased from 11.6 to 41% compared with conventional stripline-to-waveguide transition. The measured results agree well with simulated ones.
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  • Hao Peng, Peng Jiang, Tao Yang, Haiyan JIN
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150165
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    A continuously tunable substrate integrated waveguide (SIW) phase shifter based on the buried varactors is proposed. A number of varactors buried within the substrate are introduced into the SIW section. Varactor diode is a nonlinear device, of which the capacitance varies with applied voltage of an exponent factor negative fractional value. The distribution of electric and magnetic fields can be changed with varied capacitance, which results in the phase-shifted. As one example, a phase shifter with four varactors is designed and implemented. Simulation and experimental results are in good agreements. The measured results show a return loss mostly better than 10 dB and an insertion loss less than 2.3 dB within a frequency range from 1.6 to 2.6 GHz (about 47.6% relative bandwidth). The maximum phase range is about 30° at the center frequency.
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  • Ic-Pyo Hong
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150185
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    In this letter, a paper-based frequency selective surface (FSS) attachable to building walls using the ink-jet printing technique is presented using the novel type of FSS at Ku-band. The proposed paper-based FSS has frequency stability for different incidence angles and polarizations and wide band-stop bandwidth. Simulation was performed using a commercial EM software to obtain the transmission loss of the structure and then the measurement results of the fabricated one were compared. The comparisons between the simulation and measured results show good agreements.
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  • Qing Hua, Zehong Li, Xi Qu, Bo Zhang, Yuxiang Feng
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150189
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 17, 2015
    JOURNALS FREE ACCESS
    This paper presents a high reliability high voltage driver integrated circuit (IC), which has been designed and fabricated for half bridge inverter drive of the intelligent power module (IPM). By utilizing the 1.0 µm 650 V high voltage bipolar CMOS DMOS (BCD) on silicon-on-insulator (SOI) process technology combined with modified level shift circuit, the proposed high voltage driver IC offers an improved immunity to di/dt induced substrate noise, with a negative voltage undershoot down to −50 V which is about 1.5 times of the maximum allowable value of the conventional high voltage driver ICs at 100 °C, thus delivers higher reliability. Furthermore, this device also needs ultra-low quiescent supply currents and offers high driver capability (source 200 mA, sink 300 mA). In addition, this device can operate at a high temperature up to 175 °C and features higher breakdown voltage and lower leakage current than conventional high voltage driver ICs.
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  • Xiaoli Xi, Yun Fang, Jiangfan Liu, Zhongbo Zhu
    Type: LETTER
    Subject area: Electromagnetic theory
    2015 Volume 12 Issue 7 Pages 20150191
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    A stretched-coordinate (SC) based complex-frequency-shifted perfectly matched layer (CFS-PML) is presented for the two-dimensional Weighted-Laguerre-polynomials (WLP) finite-difference time-domain (FDTD) method. The proposed CFS-PML is background medium independent, and can be easily extended to dispersive medium. Numerical examples show the effectiveness of the proposed CFS-PML in truncating both air and dispersive medium.
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  • Juan Ramon Rodriguez-Rodriguez, Jacinto Torres-Jimenez, Luis Alberto C ...
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2015 Volume 12 Issue 7 Pages 20150197
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    Actually the Dual Active Bridge converter (DAB) is emerging as a key technology for applications in systems with DC-DC conversion stages, such as; electric vehicles, solid state transformers, batteries charge and DC grids interconnection. In this paper a novel modulation method for Dual Active Bridge (DAB) Converters, called Equivalents Values Modulation (EVM) is proposed. The main characteristic of EVM is the bidirectional transfer flow of active current without generating reactive currents or return currents, in both DC ports and in all operation range of the converter. This characteristic allows overcoming the actual limitations of the most significant modulation techniques for DAB converters as SPCS, DSPCS and Independent Surfaces, thus deriving the following advantages: 1) reduce the stress of current semiconductor devices, 2) minimizes peak to peak currents at the ports of DC converter and 3) reduces the RMS current in the transformer. The Laboratory experimental results, mathematical models and simulations show that the modulation method EVM, is the most suitable for controlling the power flow between the two ports of DC.
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  • Minh-Thien Hoang, Nobuyuki Sugii, Koichiro Ishibashi
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20150206
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    This paper presents a receiver design with the on-off keying (OOK) modulation at 315 MHz frequency. In this design, we propose a new architecture for the receiver to achieve low complexity with a solution to reduce total power consumption significantly. The operation of the proposed architecture is verified using available RF front-end circuits and a field-programmable-gate-array (FPGA) device. Circuit of the receiver is designed by using SPICE models of 65 nm Silicon On Thin Buried Oxide (SOTB) CMOS technology. By simulation, the receiver achieves −76 dBm sensitivity, consumes 27.6 µW from 1 V supply voltage with data rate up to 200 Kbps.
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  • Zhe-Yang Huang, Chun-Chieh Chen, Chung-Chih Hung
    Type: LETTER
    Subject area: Integrated circuits
    2015 Volume 12 Issue 7 Pages 20150207
    Published: 2015
    Released: April 10, 2015
    [Advance publication] Released: March 23, 2015
    JOURNALS FREE ACCESS
    A differential VCO with differential push-push frequency doubler for dual-band application is proposed. The dual-band VCO (DB-VCO) adopts the tunable −Gm to optimize the wide tuning start-up condition. The proposed DB-VCO was implemented in 180-nm CMOS process. The DB-VCO provides a fundamental center frequency at 4.476 GHz and a double frequency at 8.985 GHz. A tuning range of fundamental frequency is 1.125 GHz (3.928 GHz–5.053 GHz), and a tuning range of the double frequency is 2.257 GHz (7.856 GHz–10.113 GHz) with maximum control voltage of 1.0 V can be achieved. The phase noise is −96.0 dBc/Hz at 1 MHz offset from center of the DB-VCO fundamental frequency. And the phase noise is −86.4 dBc/Hz at 1 MHz offset from center of the DB-VCO double frequency. The power dissipation of the DB-VCO core is 6.6 mW through 1.0 V supply voltage. The active area is 0.09 mm2.
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