Abstract
This paper presents an ultra-high-speed correlation processor for FPGA (Field-Programmable Gate Array) which is based on MDF (multiple-path delay feedback) pipelined FFT (fast Fourier transform) architecture. In order to decrease the resource cost and processing delay, the FFT processor is based on DIF (Decimation in Frequency) decomposition method, and the IFFT processor is based on DIT (Decimation in Time) decomposition method. The data input and output of the correlation processor are both in natural order. The main clock speed of the processor FPGA implementation can be higher than 200 MHz and is able to process continuous complex input at more than 1.6 Gsps (giga samples per second).
