A state-of-the-art energy-efficient switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed in this letter. With this proposed switching scheme, the average switching energy can be reduced by 98.8% compared to the conventional approach, and 75% of the chip area can be saved. While combining with an integer-based split-capacitor structure, both the average switching energy and chip area can be approximately reduced further by half. Yet, nonlinearity analysis and Monte Carlo simulation indicate that perfect linearity is still maintained.

View full abstract

This paper presents a design strategy of eliminating signal degradation for memristor ratioed logic (MRL) gates. Based on the strategy, a novel MRL-based one-bit full adder is proposed. The inverters in circuit can effectively eliminate the degradation and restore signal integrity. To evaluate the effectiveness of the proposed one-bit full adder, an eight-bit full adder is demonstrated as a study case. Compared to the previous MRL-based standard cell design, the proposed circuit can reduce 11.1% memristor cells, 22.2% CMOS transistors, 38.9% vias, 58% power. Compared to the previous MRL-based optimized design, the proposed design can reduce 11.1% memristor cells, 12.5% CMOS transistors, 98.1% power, 98.1% energy.

View full abstract

On-chip global wires are speed and power bottleneck in state-of-the-art chips. AC coupling technique is an efficient way to reduce interconnection delay and power. This paper proposes a new capacitive-resistively driven AC coupling global link. Bandwidth performance of the proposed wire is analyzed and an optimization algorithm for capacitive-resistively driven wire is presented. Simulation results show that our optimization methodology can improve the bandwidth. By applying our optimization algorithm, data rate can be improved from 2 Gb/s to 2.5 Gb/s in the implemented transceiver circuit. The proposed optimization algorithm can be applied in high speed global communication.

View full abstract

A fully-integrated dual-band CMOS LC voltage-controlled oscillator (VCO) is presented. A fourth-order passive LC resonator configurable by a MOS switch is designed and adopted. Fabricated in a 0.18 µm standard CMOS, the dual-band VCO is capable of operating in 2.53∼2.92 GHz (low-band) and 4.76∼5.33 GHz (high-band). The measured output phase noises of the VCO operating at 2.77 GHz and 5.01 GHz at 1 MHz offset are −121.51 dBc/Hz and −115.05 dBc/Hz, respectively. The VCO dissipates 1.85 mW at both the low- and high-band from a supply of 1.2 V.

View full abstract

3DFTL is a demand-based flash translation layer (demand-based FTL) that can withstand caching data loss due to unexpected events such as power-loss. Its mapping table in the flash memory is designed with the capabilities of being instantaneously updated with zero additional write operations. Moreover, the average cache miss penalty of 3DFTL is also lower than previous demand-based FTLs. As a result, not only the mapping table of 3DFTL guarantees data consistency, but 3DFTL also shows 16.42% decrease in terms of the average system response time comparing with the DFTL.

View full abstract

This paper presents an ultra-high-speed correlation processor for FPGA (Field-Programmable Gate Array) which is based on MDF (multiple-path delay feedback) pipelined FFT (fast Fourier transform) architecture. In order to decrease the resource cost and processing delay, the FFT processor is based on DIF (Decimation in Frequency) decomposition method, and the IFFT processor is based on DIT (Decimation in Time) decomposition method. The data input and output of the correlation processor are both in natural order. The main clock speed of the processor FPGA implementation can be higher than 200 MHz and is able to process continuous complex input at more than 1.6 Gsps (giga samples per second).

View full abstract

In network-on-chip (NoC), local temperature will make failure occurs if it is too high, thereby reduces the system’s reliability. At the same time, unbalanced traffic distribution will produce local hot spots and improve local temperature, which is also easy to cause congestion of the network. In this letter, a novel NoC topology named BTorus for thermal-traffic is proposed. By using bridging form, BTorus connects the edge nodes of the Mesh topology, which is axial symmetry and beneficial to thermal-traffic balance. In addition, a traffic balanced routing algorithm is designed for BTorus, which can distribute more traffic to the edge of the chip and is good to chip’s thermal equilibrium and heat dissipation.

View full abstract

In this letter, we present a power-performance scaling in asymmetric multi-core embedded microprocessor. Asymmetric multi-core processor draws attention in embedded systems because the design tries to catch both energy-efficiency and high-performance. In this letter, we revise a multi-core power-performance scaling study with more practical parameters, and present empirical validation in a real embedded processor.

View full abstract

AMOLED displays have been emerged as a new technology recently but have a significant portion of the total power consumption in mobile devices. In this paper, we propose a novel approach which combines color transformation and dynamic voltage scaling (DVS) synergistically in the aspects of both power saving and visual quality. It adaptively selects an allowable perceptuality and saturation threshold based on the luminance value of an input image, then transforms the colors of image pixels and performs DVS while satisfying human visuality. To implement it, a board interfaced with a mobile AMOLED display module is developed. Experiments show that the proposed approach achieves on average 29.6% power saving for still images with high satisfaction to human visuality.

View full abstract

A technique for the implementation of a programmable grounded and floating resistors is presented. The grounded version of the resistor has been implemented in a standard CMOS technology, where a set of digital inputs allows the programming of the circuit. The performance of the circuit is shown by means of DC, AC, Transient and Monte Carlo simulations. Measurements on a 0.35 µm CMOS physical implementation are presented. Additionally, an application of the proposed circuit in programmable filters is described.

View full abstract

Due to the speed development of the mechanical equipment, it is important to realize the nondestructive evaluation in time to guarantee the safe and reliable operation. Distributed vibration detection is a conventional approach, but it may suffer from the disadvantages that it is complex to arrange a large amount of measuring points. On the other hand, some optimization algorithms are effective for approximate solutions. Taking into these considerations, we proposes a corresponding damage identification method to realize the damage localization by Fiber Bragg grating sensing technology with interpolation algorithm, which can create a simple method to identify the damaged region for the plate structural. In this paper, vibration detection based on some FBG sensors is built up and the optimum parameters are given. On the basis of this, interpolation algorithm is applied into vibration test and the experimental results show that localization method by the interpolation analysis is feasible to damage detection and it has better detection effect for a thin steel plate.

View full abstract

Retraction notice.

View full abstract