Structure optimization for timing in nano scale FinFET

Abstract

This paper suggests a methodology to model and optimize parasitic capacitance and resistance on nano-scale FinFET devices in terms of timing. We suggest to optimize the gate spacer thickness to minimize signal propagation delay. Due to its own 3D construction, FinFET accompanies large parasitic resistance (R) and capacitance (C) elements. It brings the larger signal delay impact on the parasitic compared to the conventional planer MOS FET devices. We reveal that the spacer thickness dependence of the RC elements results in a minimal value in the signal propagation delay. The experimental results show that the signal propagation delay can be improved up to 10% in 16 nm era FinFET circuits with controlling the spacer thickness.