A linear voltage regulator (LVR) with high electromagnetic immunity (EMI) was designed by taking voltage reference generated by temperature independent current and EMI feedback control strategy. The proposed circuit was implemented using a HV-BCD technology for vehicle applications. Simulation results show the regulator can supply 5 V output voltage with maximum 100 mA current and has good transient response performance. EMI test according Direct Power Injection (DPI) method depicts that less than 200 mV DC drift generated @10 Vpp noise injection.

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A digital calibration technique for high resolution SAR ADC with only one redundant conversion bit is presented in this paper. The proposed work employs no extra calibration DAC or input signal as calibration reference. Calibration signal is generated through switching redistribution DAC in two calibration phase, so that calibration accuracy will not be affected by input signal distribution. DAC accuracy is determined by MSB capacitors with non-binary radix, which are rounded to integer unit capacitors to get smaller mismatch. Monte carlo simulation results prove the stability of calibration accuracy to over 11b with noise and offset errors under 2% capacitor mismatch.

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Despite being proposed since more than 50 years ago, COordinate Rotation DIgital Computer (CORDIC) is still one of the most effective algorithms for elementary function calculation so far. Original CORDIC, however, suffers high latency due to its nature of unvarying number of rotations. As a result, a low-latency hybrid adaptive (HA) CORDIC is proposed in this paper. Firstly, adaptive angle selection decreases total iterations up to 50% with respect to higher accuracy of results. Secondly, hybrid architecture including fixed-point input and floating-point output reduces the total hardware utilization and enhances the dynamic range of final results. Lastly, parallel and pipeline processing together with resource sharing technique allow the design to operate fully at 175.7 MHz with low resource consumption — 1,139 LUTs and 489 registers.

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The loss uniformity of an arrayed-waveguide grating router was improved by employing an interleave-chirped arrayed-waveguide grating, without increasing the maximum loss. We fabricated a 16 × 16, 50-GHz channel-spacing, interleave-chirped arrayed-waveguide grating router for use in 1-µm wavelength band communications. The minimum loss, the maximum loss, and the loss uniformity were 5.4 dB, 7.0 dB, 1.6 dB, respectively.

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Complete complementary sequence (CCS) has ideal correlation performance along the zero Doppler axis. However, its correlation property is extremely sensitive to the Doppler shift. In this letter, by employing a sequential quadratic programming (SQP) optimization method, a novel design of the Doppler resilient CCS is presented for multiple-input multiple-output (MIMO) radar. Compared to the existing methods, this design can reduce the range sidelobes associated with a matrix-valued ambiguity function without restrictions on the waveform number, the pulse number and the waveform length. In addition, the superior orthogonality of CCS can also be achieved. Several numerical examples are provided to demonstrate the effectiveness of this design.

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In this paper, we propose a novel hardened latch to mitigate the SEU. The combination of the circuit structure and layout placement is adopted to enhance the multiple nodes upset tolerance. This latch consists of a normal D latch and a typical DICE latch. Different from the TMR latch, this latch can mitigate the charge collection on two transistors. HSPICE simulation results present that there only exit four sensitive transistor pairs in this latch. Compared to the typical DICE and DMR latch, the sensitive transistor pairs are largely reduced. And by adjusting the layout placement, these sensitive transistor pairs are separated from each other as much as possible. From the view of the layout, it is almost impossible for charge collection on the sensitive transistor pairs in our proposed latch.

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This paper suggests a methodology to model and optimize parasitic capacitance and resistance on nano-scale FinFET devices in terms of timing. We suggest to optimize the gate spacer thickness to minimize signal propagation delay. Due to its own 3D construction, FinFET accompanies large parasitic resistance (R) and capacitance (C) elements. It brings the larger signal delay impact on the parasitic compared to the conventional planer MOS FET devices. We reveal that the spacer thickness dependence of the RC elements results in a minimal value in the signal propagation delay. The experimental results show that the signal propagation delay can be improved up to 10% in 16 nm era FinFET circuits with controlling the spacer thickness.

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