Dual SPDT/SP3T SOI CMOS switch adopting alternative bias strategy with enhanced performance compared to the conventional case

Abstract

A dual single-pole double-throw (SPDT)/single-pole three throw (SP3T) distribution switch without the employment of negative voltage generator (NVG) for multi-mode multi-band applications has been designed and fabricated in a 0.18 µm silicon-on-insulator (SOI) CMOS process. To reduce power dissipation and prevent the noise from affecting the RF signal, an alternative bias strategy driven only by the positive voltage generator (PVG) is presented. Besides, LC impedance matching network are designed in both series and shunt branch to improve the insertion loss (IL) and isolation, respectively. For comparing the potential performance distinction, a switch version with conventional negative bias method is also implemented, which shows an IL of 0.41/0.65 dB and minimum isolation of 26.9/23.6 dB at 0.9/1.9 GHz, respectively. The presented switch adopting alternative bias scheme achieves improved IL of 0.37/0.53 dB and minimum isolation of 24.2/32.5 dB at 0.9/1.9 GHz, respectively. Both cases reveal comparative power handling capability and harmonic performance, while the active current consumption in the stand-by mode is significantly reduced with the new bias strategy.