Abstract
A temperature-dependent power-law model to simulate the pulsing EOS breakdown in CMOS integrated circuits (ICs) was proposed and evaluated in this study. It is a logarithm form of power-law model inversely related to the temperature. Fitting the results from the stressing of different commercial ICs with the grounded-gate NMOS (GGNMOS) ESD circuits by the electrical pulses indicated that the new model displayed comparable accuracy to the traditional E model/thermochemical model at constant/room temperature. When temperature changed, however, the new model had a better relationship in regression. The temperature-dependent power-law model could be used to evaluate the EOS window design of integrated circuits and be implemented into the components classification for the assembly line’s quality control.
