A temperature-dependent power-law model to simulate the pulsing EOS breakdown in CMOS integrated circuits (ICs) was proposed and evaluated in this study. It is a logarithm form of power-law model inversely related to the temperature. Fitting the results from the stressing of different commercial ICs with the grounded-gate NMOS (GGNMOS) ESD circuits by the electrical pulses indicated that the new model displayed comparable accuracy to the traditional E model/thermochemical model at constant/room temperature. When temperature changed, however, the new model had a better relationship in regression. The temperature-dependent power-law model could be used to evaluate the EOS window design of integrated circuits and be implemented into the components classification for the assembly line’s quality control.

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The main aim of this paper is to explain the generation technique of application specific function units (FUs) for reducing the number of instructions in Luby Transform (LT) codec processor. For this reason, Transport Triggered Architecture (TTA) is taken as an active processor template for designing a high-speed TTA-based LT codec processor using TTA-based Co-design Environment (TCE) tool. In this design, processor architectures named as P₁, P₂, P₃, P₄, P₅, and P₆ are generated to gradually improve the performance of the TTA processor. P₆ took only 4,466 cycles and 43 ms to simulate an LT codec system. In this paper, P₆ of the TCE tool took only a single iteration to generate the decoded signal.

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In this paper, an interface circuit for a three-axis digital tunneling resistance-type magnetic sensor in a standard 0.5 µm CMOS technology is presented. The weak signal detection is achieved by the chopper instrumentation amplifier. The conversion between analog and digital is achieved by the fully differential fourth-order forward Sigma-Delta modulator. The output zero-bias of magnetic sensor is corrected by digital auto-offset circuit. The design and fabrication of tunneling resistance-type magnetic sensor interface ASIC with digital output have been achieved by the research. The performance of magnetic sensor is shown as below: the sensor is at 5 V operating voltage, the value of consumption is only 120 mW; the nonlinear of the sensor is 0.1%FS; the zero reference output is less than 10 nT; the equivalent input noise density is less than 0.13 nT/Hz^1/2 (at 10 Hz).

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In this paper, a scalable high-performance multi-match priority encoder (MPE) for information retrieval is presented. This approach deploys a new design architecture to construct the large-sized MPEs by using an 8-bit priority encoder as a basement. The experiments in an 8-bit MPE, 64-bit MPE, and 2,048-bit MPE prove that the achieved throughputs are 1.5 times, 1.7 times, and 1.4 times as high as those of previous works. Furthermore, a 4,096-bit MPE is fully operational in an information retrieval system and is capable of returning one match per clock cycle. At the operating frequency of 75 MHz, the processing time in worst and best case are 54.6 µs and 0.03 µs, respectively.

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In this paper, a parameter design method of a sliding mode controller with a hysteresis band is proposed for buck converter application, which is based on the proper analysis of the controller parameters’ influences on existence condition, conduction mode and transient performance. This work discovers the fact that the trajectory of the closed loop system will end at an undesired limit cycle or equilibrium in discontinuous conduction mode, and establishes the mathematical relationship between the system overshoot and the sliding coefficient α. Next, in order to keep operating in continuous conduction mode and have a superior steady-state and transient performance, the upper limit of the hysteresis band border δ, the upper and lower limit of α are given accordingly. Finally, The effectiveness of the given design method is validated by simulation and experiment for steady-state and transient responses.

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A high performance interface circuit of sigma-delta accelerometer with low harmonic distortion used many kinds of circuit processing techniques is presented in this work. Multi-bit, dynamic element matching, correlated-double-sampling and electrostatic force feedback linearization circuit are used simultaneously in order to achieve the design indicators. Because of the usage of multi-bit, the design to operational amplifier (OPA) becomes easier, and only a single-stage folded-cascode amplifier is used in the modulator, the OSR is only 64. It highly reduced the difficulty of circuit. The test results indicate that the chip area is only about 10 mm² and the power dissipation is 10 mW with a sampling frequency of 60 kHz. The dynamic range (DR) of the system can be lower than −130 dB, the SNR and SNDR reach to −120 dB and −110 dB respectively with a resolution about 17 bits when referred to 3g full scale DC acceleration under CMOS 0.5 µm process. The dc nonlinearity of it is 0.2%. This paper realizes an approach which can both simplify the design of the interface circuit and improve the performance of it.

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A new true time delay line (TTDL) using a stepped impedance (SI) structure is proposed for compact and wideband TTDLs in GaAs MMICs. An equivalent circuit model and a dispersion equation for the proposed SI-TTDL are also presented. Experimental verification and comparison with a conventional design are provided. The group delay of the proposed SI-TTDL is substantially increased up to approximately twice of a conventional microstrip transmission line in GaAs MMICs.

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An optimized latency model and a write speed adjustment scheme are proposed to accelerate master-slave databases launched on LDPC-induced solid state drives. To the best of our knowledge, no prior work has been published to systematically study the utilization of read/write latency model on LDPC-induced master-slave databases and the impact of fast write operations on databases reliability. Experimental results show that the proposed MFW-SFR approach outperforms traditional ones with a 57.11% reduction of average read latency time on slave sites and a 33.23% reduction of average write latency time on master sites.

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A UHF RFID tag chip solution with a new oscillator calibration scheme and an EEPROM solution with memory capacity as big as 16k bits was presented. The new calibration scheme adopts a calibration command compatible with EPC Protocol, then, a field and low cost oscillator calibration is realized. To reduce the read power of the EEPROM when the storage capacity is increased to 16k bits, a global power management strategy is adopted. Thus, the capacitance load for read operation is reduced, which will result in low power consumption, and the total current consumption for the read operation is 2.26 µA. The proposed calibrated oscillator and 16k bits EEPROM were then integrated and verified in a full UHF RFID tag chip. The achieved read communication range is 3 m. The test results show that the calibration error of the oscillator is 5.7%, which can be further improved by adopting a large current switch array with each current switch carry smaller calibration current I_ref/M.

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The time varying root locus (TVRL) method has been used for investigating the transient analysis of a quadrature oscillator circuit with undesired operating points. The TVRL trajectory of the dominant pole corresponding to the time varying periodic solutions obtained by SpectreRF has been analyzed to predict the sinusoidal and relaxation oscillation mechanism. The numerical QZ algorithm has been practiced to compute the characteristic roots relative to periodic steady-state (PSS). The proposed circuit is analyzed with TVRL to check if it avoids the relaxation process and confirms the proper sinusoidal operation of oscillator or not.

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This paper presents an efficient architecture for performing 128 points to 1M points Fast Fourier Transformation (FFT) based on mixed radix-2/4/8 butterfly unit. The proposed FFT architecture reduces the computation cost by taking the advantage of the radix-8 FFT algorithm while remaining compatible with sequences whose data length is an integral power of 2. Further optimizations for reconfigurable application specified processor are developed. First, we propose a separated radix-2/4/8 butterfly unit which is more flexible than an entire radix-2/4/8 butterfly unit; second, for the sequences longer than 256K points, an efficient 2-epoch FFT solution is realized. This FFT architecture is implemented in a reconfigurable application specified processor. The computation time of our architecture is 676 us and 14.8 ms for 128K and 1M points FFTs respectively.

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An efficient digital calibration technique for timing mismatch in time-interleaved ADCs is presented. It depends on the phase detection between a reference clock and the sampling clock of each sub-ADC in TIADC system. A method of variable delay line is used to compensate the timing mismatch. The mismatch detection and compensation form a feedback loop and can achieve a real-time tracking and correcting. Simulation results showed that this technique can have the timing mismatch calibrated quickly and correctly within the entire Nyquist sampling frequency by the virtue of a smaller hardware, and can be applied to any number of TIADC.

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2T-2MTJ STT-MRAM suffers from the intrinsic stochastic switching behaviors of MTJ, “source degeneration” and leakage current problem of its access transistors, which could cause erroneous operations including write error and hold error. To mitigate those erroneous operations, Dynamic Voltage Threshold based High Voltage Threshold NMOS (HVT-nDTMOS) is used as access transistors of 2T-2MTJ to increase writing current and reducing leakage current. Simulation results show that the optimized design reduces write error rate by about 13.3% and 0.062‰ reduction in hold error rate for each memory cell on the same condition of cell area and operating scheduling, compared with traditional 2T-2MTJ structure.

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