Power-mode-aware buffer synthesis for low-power clock skew minimization

Abstract

The use of multiple power modes is an effective method for low power. In the clock tree of a multi-power-mode design, power-mode-aware buffers (PMABs) are used for removing the clock skew in different power modes. For each voltage mode of a module, its corresponding delays in the PMABs are designed to align with a global clock latency value. However, the impact of the global clock latency value on the power consumption has not been well studied. In this paper, we demonstrate that different global clock latency values may result in different power consumptions. Based on this observation, we propose a mixed integer linear programming approach to minimize the power consumption by synthesizing the PMABs with the global clock latency value considered. Compared with the previous work, benchmark data show that the proposed approach can reduce 18.31% power consumption of PMABs.