Due to ever-increasing gap between (1) the tester-channel and scan-shift frequencies, and (2) the wafer-level and package-level test frequencies, the tester-channel frequency is underutilized for stacked-ICs. Thus, we present a novel time-multiplexed test access architecture for SICs that complies with P1838 and it significant reduces test time, which reduction is observed on a synthetic SIC based on ITC’02 benchmark SoCs.
Random circuit breaker (RCB) model is a powerful tool to investigate the formation and rupture processes of conductive filaments which occur in unipolar memristor devices. However, the existing RCB models do not integrate the time and thermal parameters, which downgrades significantly the model accuracy in emulating the dynamics of conductive filaments under pulse stimulus. Meanwhile, current research lacks detailed discussions about the above-mentioned problems. In this paper, a SPICE-based optimized RCB model is proposed to explore the unipolar resistive switching characteristics of memristor devices under pulse stimulus. Compared with the original RCB model, the set and reset transitions of each breaker in the proposed model are assumed to be dominated by the thermal heat, which introduces time variable by cascading the thermal equivalent circuits on the original main breaker network and thus allows to explore the filament formation and rupture dynamics along with time. It can simulate all unipolar memristor device operations realized by the original RCB model and is accurate enough to interpret effectively the novel features arising from pulse stimulus such as nonlinear current-voltage relation, multi-states storage capacity, etc.
A proposed transconductance enhancement technique for bulk-driven OTAs working in weak inversion is presented in this paper. The basic idea is to use a bulk-driven input differential pair employing the auxiliary amplifier and positive feedback technique to enhance transconductance, which improves the enhancement ratio of transconductance from (n + 1)/(n − 1) to (n + 2)/(n − 1). The proposed amplifier based on the mentioned technique is simulated on UMC 180 nm process with the help of Spectre. The simulation results demonstrate that the transconductance of the bulk-driven OTAs working in weak inversion improves almost 50% with just a little increased power consumption compared to the conventional counterparts.
Graphene has emerged as one of the best novel materials for enhancement of various optical devices due to its exceptional light-matter interaction and optical properties. In this paper we focus on the integrated graphene optical modulator on a silicon waveguide, and show that by choosing specific design parameters of the device, we can achieve performances which surpass the previously reported graphene, and even all silicon modulators in speed, energy consumption and footprint. We substantiate our findings through numerical simulations and provide a deeper qualitative insight into the light matter interaction in graphene coated silicon waveguides.
Analog type radio over fiber (RoF) link transports radio frequency (RF) signal composed of different kind of frequency. Although previous papers have reported the transmitting multiple frequency signals using single wavelength without overlapping in electrical frequency domain, this paper assumes seriously contaminated channel for transmitting RF signal so that RF signal locates center frequency in main lobe of baseband (BB) signal. Specifically, this paper proposes RF signal transmission with 10 Gbps optical BB signal. Since RF signal is superimposed onto the optical BB signal, no additional light source is required. In addition, RF signal is naturally bandpass-sampled by random nonuniform sequence, therefore stochastic analysis is required. This paper derives error vector magnitude (EVM) of digitally modulated RF signal when the signal is simply regenerated by using bandpass filter. It is shown that theoretical analysis agrees with experimental results.
The use of multiple power modes is an effective method for low power. In the clock tree of a multi-power-mode design, power-mode-aware buffers (PMABs) are used for removing the clock skew in different power modes. For each voltage mode of a module, its corresponding delays in the PMABs are designed to align with a global clock latency value. However, the impact of the global clock latency value on the power consumption has not been well studied. In this paper, we demonstrate that different global clock latency values may result in different power consumptions. Based on this observation, we propose a mixed integer linear programming approach to minimize the power consumption by synthesizing the PMABs with the global clock latency value considered. Compared with the previous work, benchmark data show that the proposed approach can reduce 18.31% power consumption of PMABs.
We demonstrate simultaneous femtosecond pulse generation at 1.55 and 1.07 µm using a passively mode-locked Er- and Yb-doped fiber laser whose two ring cavities share the same SWNT saturable absorber. Pulse widths as short as 270∼290 fs were simultaneously obtained at both wavelengths.
Due to the off-chip I/O pin and power constraints of GDDR5, HBM has been proposed to provide higher bandwidth and lower power consumption for GPUs. In this paper, we first provide detailed comparison between HBM and GDDR5 and expose two unique features of HBM: dual-command and pseudo channel mode. Second, we analyze the effectiveness of these two features and show that neither notably contributes to performance. However, by combining pseudo channel mode with cache architecture supporting fine-grained cache-line management such as Amoeba cache, we achieve high effciency for applications with irregular memory requests. Our experiment demonstrates that compared with Amoeba caches with legacy mode, Amoeba cache with pseudo channel mode improves GPU performance by 25% and reduces HBM energy consumption by 15%.
With a growing number of cores integrated in a single chip, the efficiency of inter-core direct memory access (DMA) transfers has an increasingly significant impact on the overall performance of parallel applications running on network-on-chip (NoC) processors. In this paper we propose HyDMA, a low-latency inter-core DMA approach based on a hybrid packet-circuit switching NoC. With dynamic setup and lengthening of circuit channels composing of bidirectional links, HyDMA can achieve both high flexibility of packet switching and low communication latency of circuit switching for concurrent DMA transfers. Experimental results prove HyDMA exhibits high efficiency with marginal hardware overhead.
This letter presents a high efficiency, and small group delay variations 12–24 GHz fully-integrated CMOS power amplifier (PA) for quasi-millimeter wave applications. Maximizing the power added efficiency (PAE), and minimizing the group delay variations in a wideband frequency range are achieved by optimizing the on-chip input, output, and inter-stage matching circuits. In addition, stagger tuning is employed for realizing excellent gain flatness. A two-stage CMOS PA using the proposed methodology is designed and fabricated in 0.18 µm CMOS technology and tested. A measured power gain (|S21|) of 10.5 ± 0.7 dB and a measured small group delay variation of ±20 ps over the frequency range of interest are achieved. The PA shows a maximum measured PAE to be 26 % with DC power consumption of 50 mW.
In this paper, a novel accurate Schiffman-type (S-type) section design approach is presented for microstrip line Wilkinson power divider. S-type section replaces straight 90° transmission line with compact circuit size and easy fabrication, isolation condition between two output ports is also maintained in microstrip line structure. Mathematical equations for S-type section are derived from even- and odd-mode equivalent circuit analysis, and several selected examples have been proved that: through adjusting the even- and odd-mode characteristic impedances and their electrical lengths of S-type section, proposed Wilkinson power divider provides perfect matching in microstrip line structure; in other words, S-type section could provide self-compensation in microstrip line structure, no extra compensation structure is needed. In experiment, one circuit was fabricated, and experimental results showed good agreement with theoretical results.
To improve the efficiency of network, virtualization has developed by sharing the same physical network’s resources for different users and applications. As one of the substrate networks, elastic optical network (EON) is expected to be used for the virtualization due to its flexibility and effectiveness. In this letter, we propose a virtual network mapping algorithm called resource and load aware algorithm based on ant colony optimization (RL-ACO), which considers the load jointly with spectrum continuity and spectrum contiguity during the node mapping stage. The variation of node availability rank is defined in the process of link mapping which helps to decrease the blocking ratio of virtual network requests. Simulation results show that RL-ACO not only reduces the blocking probability and the occupied frequency slots, but also balances the link load.