Universal closed-form expressions for the inductance of tapered through silicon vias (T-TSVs) based on vector magnetic potential

抄録

This paper proposes novel formulas for the calculation of the parasitic inductance of Tapered-Through Silicon Vias (T-TSVs), considering the TSVs located in adjacent layers. The formulas can not only be reduced to calculate the self-partial inductance and mutual-partial inductance of T-TSVs located in the same layer but also be used for cylindrical TSVs when the slope angle is 90°. The comparison between the results of the proposed formulas and Ansoft Q3D shows that the proposed formulas have very high accuracy with a maximum error of 2.5%.