IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
A DMR logic for mitigating the SET induced soft errors in combinational circuits
Zhang JiajinYang HousenDu YankangGao QuanPeng LinZhang YueLichang Chen
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2016 Volume 13 Issue 2 Pages 20150927

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Abstract

In this paper, a novel dual module redundancy (DMR) logic circuit structure is proposed to harden the standard cells in the large combinational circuits. Three-dimensional TCAD simulation results present that this hardening structure can ultimately eliminate the SET pulse. Based on this DMR logic circuit structure and the layout placement adjustment technique, the partial hardening approach is used to harden the large combination circuits.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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