IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Volume 13 , Issue 2
Showing 1-12 articles out of 12 articles from the selected issue
LETTER
  • Jing Qiu, Xiaoyan Xiang, Zhijian Chen, Jianyi Meng, Yong Ding
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2016 Volume 13 Issue 2 Pages 20150493
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: January 07, 2016
    JOURNALS FREE ACCESS
    Conventional processors that execute a single instruction at a time are easy to implement but lack the power efficiency. This paper presents a novel hardware-software co-designed method to save power consumption for ECG applications. The software generates block instruction which is comprised of several atomic operations, reduces the instruction memory space, and merges memory operations within a block. The hardware executes instructions block by block, eliminates redundant fetching and decoding operations. The experiments indicate that the proposed design methodology can reduce the active power consumption and code size by 40% and 55% relative to CK802 (a conventional processor).
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  • Zhichao Zhang, Anh Dinh, Li Chen
    Type: LETTER
    Subject area: Integrated circuits
    2016 Volume 13 Issue 2 Pages 20150917
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 18, 2015
    JOURNALS FREE ACCESS
    This paper presents a low-noise amplifier (LNA) design for multifunction receiver front-end. Based on the conventional noise cancelling technique, a gain-enhanced noise cancelling structure is presented and the effect of gain-enhanced stage is discussed. The wideband input matching is realized by a current-reuse common-source stage with an active feedback structure to alleviate the tradeoffs between NF, gain, and bandwidth. A peaking gate inductor is inserted to improve gain flatness and bandwidth of the designed amplifier. The proposed LNA was implemented in the 0.130 µm CMOS technology. It achieves a S11 of <−10 dB in a wide frequency range 0.1–8 GHz and a gain of >14 dB with a 14.5 dB peak. Over this range, a minimum NF of 2.6 dB is achieved and the total power consumption is only 17 mW from a power supply of 1.2 V. The results indicate that the proposed structure effectively improves the gain of conventional noise cancelling technique while the noise elimination and wideband input matching are maintained.
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  • Zhang Jiajin, Yang Housen, Du Yankang, Gao Quan, Peng Lin, Zhang Yue, ...
    Type: LETTER
    Subject area: Integrated circuits
    2016 Volume 13 Issue 2 Pages 20150927
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 18, 2015
    JOURNALS FREE ACCESS
    In this paper, a novel dual module redundancy (DMR) logic circuit structure is proposed to harden the standard cells in the large combinational circuits. Three-dimensional TCAD simulation results present that this hardening structure can ultimately eliminate the SET pulse. Based on this DMR logic circuit structure and the layout placement adjustment technique, the partial hardening approach is used to harden the large combination circuits.
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  • Jinguang Hao, Kai Wang, Wenjiang Pei, Yili Xia
    Type: LETTER
    Subject area: Electron devices, circuits, and systems
    2016 Volume 13 Issue 2 Pages 20150938
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 18, 2015
    JOURNALS FREE ACCESS
    A high-accuracy baseband signal processing system of digital phosphor technology for real-time spectrum analysis is proposed based on fast filter bank (FFB). The modular instruments based platform is utilized to verify the performance of the proposed scheme implemented with field-programmable gate array (FPGA) module. With the single-tone signal as a test signal, the experimental results show that the proposed scheme can improve the accuracy of the real-time spectrum analysis at the cost of slightly higher complexity than that of fast Fourier transform (FFT) based scheme.
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  • Yo-Hao Tu, Jen-Chieh Liu, Kuo-Hsing Cheng, Hong-Yi Huang, Chang-Chien ...
    Type: LETTER
    Subject area: Integrated circuits
    2016 Volume 13 Issue 2 Pages 20150950
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 22, 2015
    JOURNALS FREE ACCESS
    This paper proposes an 8-phase all-digital phase-locked loop (ADPLL) for a low supply voltage application. The proposed multi-phase digitally controlled oscillator (MP-DCO) employs two sub-feedback loops at high operational frequencies. The proposed multi-phase-based time-to-digital converter (MP-TDC) uses the multi-phase scheme, which reduces its area, and uses a time amplifier to extend the timing resolution. With a low supply voltage, the DCO and the sense-amplifier based delay flip-flop (SA-DFF) use bulk-controlled techniques to improve the performance at high operational frequencies and setup/hold times, respectively. When the ADPLL output is 1.6 GHz at 0.6 V, the RMS and peak-to-peak jitters are 3.8 ps and 33.7 ps, respectively. The power consumption and core area are 9.1 mW at 1.6 GHz and 0.036 mm2 in a 90 nm CMOS process, respectively. Thus, this clock generator is useful for low power systems.
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  • Seung-Ho Lim, Woo Hyun Ahn
    Type: LETTER
    Subject area: Storage technology
    2016 Volume 13 Issue 2 Pages 20150976
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 22, 2015
    JOURNALS FREE ACCESS
    NAND Flash memory storage is widely used in computing systems. In General, there exists mismatch between logical address and physical address in Flash storage, and these address translations are managed by Flash Translation Layer (FTL). Due to its management, logically invalid data is considered as physically valid at some parts in Flash device, which causes additional overhead. The physically valid area being logically invalid area can be invalidated by TRIM or discard command, however, too many discard commands degrade throughput. In this paper, we propose a bitmap-based discard operation which can decrease the number of runtime discard commands. According to the proposed scheme, hundreds of separated region can be discarded all at one bitmap-based discard command.
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  • Yu Guo, Xiaozhou Liu, Haodong Wu, Shanwen Hu, Guojun Wang, Guann-Pyng ...
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2016 Volume 13 Issue 2 Pages 20150990
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 18, 2015
    JOURNALS FREE ACCESS
    A novel design for compact customizable tunable EBG (Electromagnetic Bandgap) filter is proposed. The tunable filter is implemented in RO4350 substrate using PCB (Printed Circuit Board) process with surface mounted solid-state varactors and lumped capacitors. Its frequency is tuned by adjusting applied voltages of the varactors. The filter is unique that it is capable to be tuned in customizable specified frequency range by selecting the lumped capacitors. The simulated and measured results of the proposed filter are found to be in good agreement. It is demonstrated that a two-pole filter with size of 3.20 × 3.90 × 1.52 mm3 in PCB achieving performance of a tuning range of 5.3–6.3 GHz with a 1-dB fractional bandwidth below 6.35% and a constant insertion loss of 4.4 dB ± 0.2 dB.
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  • Minshun Wu, Zhiqiang Liu
    Type: LETTER
    Subject area: Integrated circuits
    2016 Volume 13 Issue 2 Pages 20150991
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 25, 2015
    JOURNALS FREE ACCESS
    A noncoherency correction algorithm is proposed to remove the spectral leakage caused by noncoherent sampling in ADC spectral test. The coherent data is reconstructed from the original data by an additional FFT and only a few simple time domain operations. Then accurate spectral testing results can be obtained by performing normal FFT on the reconstructed data. Compared with windowing techniques, the proposed method can acquire better spectral testing accuracy without any prior knowledge. Theoretical analysis, simulation and experimental results demonstrate that the developed method can achieve the estimation accuracy comparable to that of coherent sampling method but without requiring coherent sampling.
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  • Chan-Won Park, Eui-Rim Jeong, Ji-Hoon Kim
    Type: LETTER
    Subject area: Microwave and millimeter wave devices, circuits, and systems
    2016 Volume 13 Issue 2 Pages 20150998
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: January 07, 2016
    JOURNALS FREE ACCESS
    A digital predistortion (DPD) technique to linearize multiple power amplifiers (PAs) in analog beamforming systems is proposed. The analog beamforming system considered in this paper has one digital chain and multiple PAs/antennas controlled by phase shifters. Due to the system configuration, a single DPD should linearize the multiple PAs. To design the DPD, this paper introduces a cost function, squares of the sum of errors for all the PAs. The DPD solution minimizing the cost function is found by a recursive least squares (RLS) algorithm. Experimental results with commercial PAs show that the proposed DPD can effectively linearize multiple PAs.
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  • Jiangping He, Bo Zhang, Gao Pan, Qing Hua
    Type: LETTER
    Subject area: Integrated circuits
    2016 Volume 13 Issue 2 Pages 20151006
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: December 18, 2015
    JOURNALS FREE ACCESS
    A novel progressive trigger (PT) method of di/dt control for MOSFET is presented in this paper. The principle of the proposed method is based on the progressive trigger current during ON and OFF states by variable channel width for MOSFET. The experimental results show that the di/dt reduces from 105 mA/nS to 57 mA/nS for OFF state, and from 110 mA/nS to 86.7 mA/nS for ON state with RON = 0.5 Ω and Vgg = 3 V. The flexibility of the method is easy to implement in integrated circuits.
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  • Hao Xiao, Huajuan Zhang, Fen Ge, Ning Wu
    Type: LETTER
    Subject area: Integrated circuits
    2016 Volume 13 Issue 2 Pages 20151025
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: January 12, 2016
    JOURNALS FREE ACCESS
    With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities, this paper presents a MapReduce-based multiprocessor system-on-chip (MPSoC) for providing efficient architectural supports to MapReduce parallel programming paradigm. We implement the proposed MPSoC in cycle-accurate SystemC and evaluate its performance using a set of representative MapReduce applications. Results show that the proposed MPSoC can achieve up to 2.1× overall performance improvement over the current general purpose multicore processors in typical MapReduce applications.
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  • Kenichiro Tsuji, Kohei Hagiwara, Tomoyuki Uehara, Noriaki Onodera
    Type: LETTER
    Subject area: Fiber optics, Microwave photonics, Optical interconnection, Photonic signal processing, Photonic integration and systems
    2016 Volume 13 Issue 2 Pages 20151029
    Published: 2016
    Released: January 25, 2016
    [Advance publication] Released: January 07, 2016
    JOURNALS FREE ACCESS
    Optical microwave or millimeter-wave generation using the beat note of two lightwaves is an attractive technique because of its advantages of frequency-tunable micro/millimeter-wave generation, high selectivity of the operation frequency, and high-speed phase switching of the generated signals owing to the photonics-based scheme. In this paper, we propose and demonstrate the simultaneous generation of two microwave signals with a precisely-controlled phase difference using the orthogonal polarization modes existing in a polarization maintaining fiber. High stability and controllability of the phase difference between the generated two microwave signals was experimentally confirmed.
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