抄録
Conventional processors that execute a single instruction at a time are easy to implement but lack the power efficiency. This paper presents a novel hardware-software co-designed method to save power consumption for ECG applications. The software generates block instruction which is comprised of several atomic operations, reduces the instruction memory space, and merges memory operations within a block. The hardware executes instructions block by block, eliminates redundant fetching and decoding operations. The experiments indicate that the proposed design methodology can reduce the active power consumption and code size by 40% and 55% relative to CK802 (a conventional processor).
