IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A MapReduce architecture for embedded multiprocessor system-on-chips
Hao XiaoHuajuan ZhangFen GeNing Wu
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2016 Volume 13 Issue 2 Pages 20151025

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Abstract

With the advent of the Internet of Things, collection and processing of large datasets on embedded systems become increasingly important. Therefore, to enable embedded processors with more data processing capabilities, this paper presents a MapReduce-based multiprocessor system-on-chip (MPSoC) for providing efficient architectural supports to MapReduce parallel programming paradigm. We implement the proposed MPSoC in cycle-accurate SystemC and evaluate its performance using a set of representative MapReduce applications. Results show that the proposed MPSoC can achieve up to 2.1× overall performance improvement over the current general purpose multicore processors in typical MapReduce applications.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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