Tri-level capacitor-splitting switching scheme with high energy-efficiency for SAR ADCs

抄録

An energy-efficient tri-level capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme is a combination of the zero-power-consumption switching algorithm and the one-side double-level switching technique. By zero-power-consumption switching algorithm, there is no switching power dissipation during the first three bit cycles. Furthermore, only one-side capacitors are switched between two reference voltages (ground and V_CM) during the remaining bit conversions, which is more energy-saving than the monotonic switching method. The proposed switching method reduces the switching energy by 50.59% compared to the Sanyal and Sun proposed one.