Design of local ESD clamp for cross-power-domain interface circuits

Abstract

To effectively protect the cross-power-domain interface circuits from electrostatic discharge (ESD) damages, a PMOS-based local ESD clamp was proposed in this work. The test circuits of prior and proposed designs have been implemented in silicon chip. The proposed design has the small chip area, low leakage current, and low peak transient voltage; therefore, it can help to reduce the overstress voltages across the interface circuits under ESD tests. With the better performances, the proposed local ESD clamp can be a better solution for cross-power-domain interface circuits.