An energy-efficient tri-level capacitor-splitting switching algorithm for successive approximation register (SAR) analog-to-digital converters (ADCs) is proposed. The proposed switching scheme is a combination of the zero-power-consumption switching algorithm and the one-side double-level switching technique. By zero-power-consumption switching algorithm, there is no switching power dissipation during the first three bit cycles. Furthermore, only one-side capacitors are switched between two reference voltages (ground and VCM) during the remaining bit conversions, which is more energy-saving than the monotonic switching method. The proposed switching method reduces the switching energy by 50.59% compared to the Sanyal and Sun proposed one.
This paper describes the design and fabrication of flexible radio-frequency inductors integrated on a polyethylene terephthalate substrate. Experimental and modeling results for the RF responses of flexible inductors are reported. Investigations and analysis have been conducted on the effects of layout and process parameters on the frequency responses of inductance, quality factor and self-resonant frequency of the spiral inductors. The influence of bending strain on the performance of spiral inductors is also investigated based on measurement and modeling results. The analysis provides guidelines for designing the flexible spiral inductors towards the flexible monolithic microwave integrated circuits on a plastic substrate.
Recently, large efforts are made to achieve high throughput for aggressive voltage/frequency scaling in Error Detection and Correction system. In this paper, a zero-cycle penalty Timing-Borrowing and Clock Token (TBCT) based error correction method is proposed. A new error masking flip-flop is designed to enable time-borrowing and a clock token system is provided to pay back the borrowed time by locally shifting the clock phase of vulnerable flip-flops on the cascaded pipeline. The TBCT error correction method and error masking flip-flop are implemented into a 3-stage industrial Chinese microprocessor in a 40 nm CMOS process. Final experiment results show the proposed method achieves 1%–6% higher throughput than clock gating method and 9%–41% higher throughput than instruction replay.
Motivated by the challenging requirements of optimal fault tolerance and real-time response in the Compact PCI (CPCI) measurement and control systems, a design of a high-availability hot-swap system based on VxWorks operating system is proposed. In addition, multiple methodologies are designed and applied to guarantee operational safety during the hot-swaps. An external experimental measurement platform is developed to analyze the reliability of the controlled entity in the hot-swap hot redundancy experimental system. The experimental results prove that this hot-swap hot redundancy system achieves highly stable performance as designed.
To effectively protect the cross-power-domain interface circuits from electrostatic discharge (ESD) damages, a PMOS-based local ESD clamp was proposed in this work. The test circuits of prior and proposed designs have been implemented in silicon chip. The proposed design has the small chip area, low leakage current, and low peak transient voltage; therefore, it can help to reduce the overstress voltages across the interface circuits under ESD tests. With the better performances, the proposed local ESD clamp can be a better solution for cross-power-domain interface circuits.
Approximate computing has drawn recent attention as it can reduce power without significantly sacrificing the output quality for arithmetic operations in error-resilient applications. However, the error characteristics evaluation often depends on time consuming random simulation and estimation. In this paper, a formal framework of evaluating approximate adders is proposed based on a theoretical model. The proposed framework can accurately measure mean squared error (MSE) and mean absolute error (MAE) without using functional simulations. An approach has been adopted to estimate the final PSNR value in terms of MSE and MAE for DCT-IDCT image compression system. Experimental results have validated the accuracy and usefulness of the framework.
Aiming at the phenomenon of poor precision locking motor control executed by the photoelectric encoder of low resolution, a method of gyro locking control based on filtering estimation is proposed. The influence of control precision on self-calibration and coarse alignment of the rotational inertial navigation system (RINS) is analyzed. The model of the control system is established and simulated. Then the control mode is applied on RINS. The results of simulation and experiments show that the precision of locking control method designed in this paper outperforms the previous scheme and the self-calibration effect of RINS has significantly improved.
The influence of the N+ floating layer on the drift doping of RESURF LDMOS is studied in this paper. By optimizing the electric field distribution, a new RESURF criterion for LDMOS with N+ floating layer is developed as: NDtS ≤ 0.83 × 1012 cm−2 (ND and tS are the drift doping and thickness, respectively). The optimal drift doping is smaller than that of Single RESURF LDMOS (NDtS ≤ 1.4 × 1012 cm−2). Both analytical and numerical results show the N+ floating layer can be used to increase the breakdown voltage of LDMOS but at the cost of a low drift doping and a large on-resistance. The effect of the N+ floating layer on REBULF LDMOS is also studied in some detail. This model can be used in the design of RESURF and REBULF LDMOS to optimize the doping concentration of the drift region.
In this paper, a new method is proposed to calculate transconductance ratio of the main and the peaking transistor of a Doherty power amplifier (DPA) which employs output matching circuits and offset lines. Cascade ABCD two-port parameters are used to analyze output section of the DPA. It is shown that output matching circuits has impact on the magnitude and the phase of the transconduction ratio. The effect of the input phase mismatch on the output power and efficiency is analyzed analytically. A 100 W dual drive Gallium Nitride (GaN) Doherty power amplifier is realized to experimentally verify the results. The drain efficiency measured as 68% at the correct phase, 65% for 30° input phase mismatch and 56% for 45° input phase mismatch.
In the initial start-up period of power converter, there is no voltage supply from auxiliary winding to pulse-width-modulation (PWM) IC. Therefore, a typical method is connected with a start-up resistor (Rstart) between bridge rectifier and IC controller for initial voltage supply. However, the Rstart would continue to consume energy even if the auxiliary voltage has been set up. The proposed scheme uses depletion-type NMOS to connect with Rstart. The start-up mechanism can be guaranteed without any additional voltage, and naturally cut off the Rstart to minimize power dissipation once the voltage of PWM IC is supplied from auxiliary winding. As a result, the outstanding standby power performance can be implemented and comply the power regulation of 5 star standards of mobile charger. Experimental results demonstrate the standby power consumption only 28.8 mW.
In this paper, we present a concurrent tri-band power amplifier by using a tri-band matching network synthesis method. At the package plane, a cross-type impedance transformer and susceptance matching network are placed in parallel to realize the desired admittance at three independent frequencies. Design equations of the different possible topologies are present based on ABCD-parameters. Then, the proposed synthesis approach is validated with the design of a tri-band power amplifier at frequency bands 0.90, 1.85 and 2.40 GHz. For a continuous-wave measurement, the peak drain efficiency is 70.0%, 67.1% and 59.8% at 0.90, 1.85 and 2.40 GHz, respectively.
Bragg scattering mechanism has been probed by a fully digital ultra-high-frequency (UHF) radar system. The system is based on studies of UHF radio wave (340 MHz) scattering from small-amplitude water waves. First-order radar cross section Doppler spectra have been measured. Comparing them with theoretical models, good agreement has been found. The amplitude ratio (dB) of the cross section between incident and reflected waves is 14.7 dB, and its deviation is 0.68%. The expectation of the normalized Doppler frequency shift of first-order peaks is 0.9850, and the deviation is 1.5%.