2016 Volume 13 Issue 23 Pages 20160810
This paper focuses on testing the setup/hold times of the internal elements in FPGAs. Using only the existing on-chip resources, this method is quite universal and low-cost for testing modern FPGAs. One clock signal is used as data input and its relationship with the other clock is directly adjusted by PLL or DCM. Global clock network is employed to transmit signals to get minimum skew and maximum flexibility. The on-chip Self-Controller detects the results according to pass probabilities automatically. This automatic method is implemented in real FPGAs. The experiments show that this method can measure setup/hold times of different elements in the FPGAs correctly: the standard deviation is 4.3 ps and the resolution is 13 ps for Xilinx Virtex-4 and Virtex-5.