This paper focuses on testing the setup/hold times of the internal elements in FPGAs. Using only the existing on-chip resources, this method is quite universal and low-cost for testing modern FPGAs. One clock signal is used as data input and its relationship with the other clock is directly adjusted by PLL or DCM. Global clock network is employed to transmit signals to get minimum skew and maximum flexibility. The on-chip Self-Controller detects the results according to pass probabilities automatically. This automatic method is implemented in real FPGAs. The experiments show that this method can measure setup/hold times of different elements in the FPGAs correctly: the standard deviation is 4.3 ps and the resolution is 13 ps for Xilinx Virtex-4 and Virtex-5.
A novel waveguide passive X-band power limiter with a compact size and simple construction is designed and tested. The proposed limiter is made with the combined structure of a band pass filter and a limiter by incorporating a PIN diode in the narrow gap region of the H-shaped resonant aperture. Single- and two-stage limiters are designed and experimented with. In particular, for the two-stage limiter structure, a miniaturization method is proposed by using an inductor-type iris as a compact inverter, and the limiter length is reduced by about 67%, compared to the conventional one.
This paper presents a capacitor-less low-dropout (LDO) regulator for on-chip mobile applications. An additional push-pull current with a capacitive coupling circuit is proposed to significantly enhance the transient response of the LDO regulator. The proposed LDO regulator can deliver an output current of 100 mA with a minimum dropout voltage of 0.4 V. The circuit was modeled and implemented in a 0.35-µm CMOS process with a die area of 0.22 mm2. The experimental results show that the LDO regulator can be recovered within 0.5 µs at a voltage spike less than 90 mV.
This paper proposes new structures of multi-stage noise-shaping (MASH) sigma-delta ADC by applying second-order noise-coupling technology to conventional MASH modulators. The proposed architectures take advantage of the extra noise-coupled path to achieve a second-order noise-shaping increase as well as save the number of active devices. Theoretical analysis and system-level simulation are given, and the implementation of the modulators is also analyzed. The new structures are suitable for broadband applications.
This letter presents a high-accuracy clock synchronization circuit, which reduces the time error between the master and slave clocks to less than 1 ns. To suppress quantization errors resulted in generation of timestamps and pulse-per-second (PPS) signals, time-to-digital converters (TDC) and digital-to-time converters (DTC) have been implemented using tapped delay lines. The proposed scheme provides a cost-effective solution for applications of clock synchronization since it works on gigabit Ethernet using copper media (1000BASE-T) without any extra clock synthesis. Experimental results show that the two nodes over network share synchronized timing within the error between −0.74 ns and 0.89 ns.
Fault-tolerant techniques are absolutely vital for large scale multiprocessor array as it suffers from frequent hardware defects or soft faults. This paper presents a satisfiability (SAT)-Based method for the reconfiguration of a two-dimensional degradable very-large-scale integration (VLSI) array with faulty processing elements (PEs). An SAT model of the target array is proposed such that the target array can be constructed by using the efficient SAT solver. For minimizing the interconnection length of the target array, we present an incomplete algorithm, to search a target array with suitable interconnection length to meet the system requirement. Our evaluations show that the proposed incomplete algorithm is efficient, which is compared with the state-of-the-art.
A 0.6 V full wave rectifier with current mode nested and periodic feedback loops is presented, for the improved dynamic range with the low supply voltage. Compared with the conventional rectifiers, the rectifier with the loops is characterized by the micro feedback loop nested in the periodic macro one, so as to enlarge the dynamic range of the current mode signal with the ultra power supply voltage. With the technique, the dynamic range of the fully rectified signal should be optimized. Fabricated with a 0.18 µm CMOS process, with the typical 0.6 V supply voltage, the minimum amplitude of the fully rectified signal reaches 10 nA with the input signal bandwidth of 10 kHz and the power dissipation of 50 nW.
This paper presents a floating point fused dot-product (FDP) unit with latency reduced. The proposed FDP unit performs the dot-product operation of four floating point numbers: ab ± cd and is implemented with dual-path algorithm. The proposed FDP is modeled in Verilog-HDL and synthesized using TSMC 65 nm technology library. Synthesis results show that our proposed FDP unit is 24∼30% faster and 36.4% less area than the fastest FDP in previous work. We also use the proposed FDP unit and our previously designed FAS (fused add-subtract) unit to implement a FFT Radix-2 Butterfly (R2BF) unit. The latency of our proposed R2BF unit is improved roughly by 34% and the area is reduced by 41.6%, compared to the fastest 2’s-complement butterfly unit.
The three-level neutral-point-clamped (NPC) inverter, which is a widely used topology of grid-connected multilevel inverters, suffers the drawback of the NP voltage drift. This paper introduced an improved predictive direct current control strategy to improve grid-connected current quality of the system. The proposed strategy uses the nearest-three-virtual-vector (NTV2) modulation strategy which can get rid of the NP voltage balance problem for any range of inverter output voltage. Since the disadvantages of a lot of calculation for NTV2 algorithm in real-time control, the vectors in other sextants are mapped into the first sextant by a simple coordinate transformation. The time derivatives of currents for each selected vectors are used to get the application times that minimize objective function. In addition, comparing with SVPWM approaches the proposed strategy have a constant switching frequency and better line current total harmonic distortion (THD), its validity is verified by the simulation and experiment.
By adopting the human visual system property, a priority-based selective bit dropping strategy to reduce DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory) power consumption is presented in this paper. The tradeoff between power consumption and output quality is explored as well. During the data flow in image processing, the original image data are first processed with our proposed strategy, from which the number of bit-‘1’ in lower part of each pixel is reduced. Then the approximate data are pushed into the DRAM and SRAM for further computation, where the refresh power consumption for DRAM is reduced due to the less bit-‘1’ in each data and the write power consumption for SRAM is also reduced due to the lower switch probability in write operation. The proposed strategy has been realized with digital logic circuits and the approximate image data are processed by the Discrete Cosine Transform (DCT) in simulation. The results show that 27.7% refresh power reduction on average for DRAM can be achieved and the SRAM also obtained 21.7% write power reduction with negligible overhead. As for the final output quality of the images, only 1.01 dB losses for Peak-Signal-Noise-Ratio (PSNR) is presented (about 3% lower than accurate processing) after the DCT processing.
We present a real-time state synchronization approach, called PIHS3TMR here, for the improvement of the real-time performance of the repairable triple modular redundancy systems. In our approach, the repaired module’s state synchronization with the other modules is performed by constructing its state directly according to the present input of the system and the present states of the fault-free modules. Experimental results show that, with very small hardware resource overhead and maximum frequency decline, the proposed approach can obtain state synchronization in one clock cycle, which is hundreds of times faster than state-of-the-art state restoration techniques for a Lion2 CPU. And there is no interruption or delay in system functionality during the synchronization process.
A novel uni-dimensional chipless displacement sensor circuit based on spurline resonators is presented. Sensor circuit design consists of two components: series of spurline resonators and a selector element. In response to displacement, the selector element slides over the spurline resonator slots that translating this movement into a corresponding change in the circuit’s frequency response. The designed circuit offers a capacity of 16 bits in the 2–4.2 GHz frequency band. Half of the bits are designated as the sensory bits, while the other half are attributed as the ID bits. The formulated sensor has a dynamic range from 0–3.75 mm and a minimum resolution of 0.25 mm. The proposed sensor is a prime candidate for deployment in smart cities for ubiquitous infrastructural health monitoring.
This paper deals the generation of chirped delay (CD) effect in microwave regime. For the purpose of achieving reflection dispersion, electromagnetic band-gap (EBG) structures with different rejection frequency are fabricated in different position by modulating the thickness of substrate. Microwave with different frequency will be reflected in different position, so non-flat reflected group delays responses can be obtained. One CD-EBG with 6–10 GHz operation frequency range is designed, fabricated and measured. Different group delay responses are obtained when feeding from different ports. Finally, temporal characteristic of the CD-EBG is studied by simulation and two chirped impulses are obtained.