Satisfiability-based method for reconfiguring power efficient VLSI array

抄録

Fault-tolerant techniques are absolutely vital for large scale multiprocessor array as it suffers from frequent hardware defects or soft faults. This paper presents a satisfiability (SAT)-Based method for the reconfiguration of a two-dimensional degradable very-large-scale integration (VLSI) array with faulty processing elements (PEs). An SAT model of the target array is proposed such that the target array can be constructed by using the efficient SAT solver. For minimizing the interconnection length of the target array, we present an incomplete algorithm, to search a target array with suitable interconnection length to meet the system requirement. Our evaluations show that the proposed incomplete algorithm is efficient, which is compared with the state-of-the-art.