抄録
The use of a multiple-input floating-gate transistor as the main element for effecting the correlation of two binary sequences is proposed and validated. A complete architecture is proposed to implement a correlating system. The algorithm is discussed and the implementation of a circuit for 256-bit sequences in 0.35 µm CMOS technology is presented as a testing vehicle. Its use is furthermore proposed as a pilot baseband signal detector for a wireless communication system. The manufactured circuit offers favorable performance with a clock signal of up to 25 MHz with a 2.3 V supply voltage and 20 mW of power consumption.
