IEICE Electronics Express
Online ISSN : 1349-2543
MSP based thermal-aware mapping approach for 3D Network-on-Chip under performance constraints
Gui FengFen GeNing WuLei ZhouJing Liu
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2016 Volume 13 Issue 7 Pages 20160082


Three dimensional Network-on-chip (3D NoC) is proposed as an effective architecture to optimize system performance. However, thermal issues bring significant challenges on 3D NoC due to high power density. In this paper, we propose a 3D matrix synthesis problem (MSP) based thermal-aware mapping approach under performance constraints for 3D NoC architecture to realize temperature equilibrium and achieve better performance. Genetic algorithm is taken in the approach to obtain the optimal placements. Experimental results show that the proposed approach can achieve a temperature deviation of 45.3% on average compared with the state of art thermal optimization approaches. Moreover, our approach achieves 9.43% power saving and 14.88% delay reduction.

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© 2016 by The Institute of Electronics, Information and Communication Engineers
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