A resilient tracking circuit for suppressing the timing variation of SRAM sense amplifier enable (SAE) signal is proposed. Pipelined replica bitline technique is used to favour the desired design. Simulation results show that the cycle time is reduced by ∼27% owing to ∼70% reduction of the standard deviation of SAE at a 1.05 V supply voltage in 28 nm CMOS technology with four-stage pipeline.

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A column readout circuit with proposed dual integration CDS for low pattern noise infrared imager is presented. By using an extra integration, the dual integration CDS effectively reduces the level of column and row noise (CN and RN) and column fixed pattern noise (CFPN) in an infrared image. In addition, a time flexible integration technique minimizes the penalty of readout time by a dual operation. Simulation of a 0.18 µm CMOS implementation suggests that CN can be reduced by 68%, RN by 71%, and CFPN by 95% compared with a column readout circuit with conventional CDS.

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This paper presents a new design of complementary metal-oxide-semiconductor microelectromechanical systems (CMOS-MEMS) infrared (IR) emitter arrays. The infrared emitter array is a key radiation source for various gas sensors. In this work, an IR emitter array has been implemented using the standard CSMC 0.5 µm 2P3M CMOS process. Three different shapes of micro emitters are designed. Heating resistor in each emitter is a moderate resistor composed of tungsten via-chain laminated in the micro structure, which is mechanically released from the substrate surface by the post-CMOS dielectric dry etching and aluminum sacrificial layer wet etching. This design shows a potential to vertically integrate CMOS circuits and MEMS IR emitter within a small footprint. In most CMOS-MEMS similar devices, on the other hand, polysilicon heating resistors were released by bulk silicon etching, which urges the IR emitter to be integrated in a coplanar CMOS circuit with a larger footprint. Thermal properties and radiation properties of the emitters under vacuum condition are calculated in a 2-step sequential simulation. Firstly, steady state temperature response and dynamic temperature response are calculated through multi-physics coupling finite element method (FEM) simulation, and thermal mass and thermal conductance of each micro emitter are derived. Secondly, dynamic radiation responses are also estimated with a Matlab program based on Plank’s radiation law. All simulation results supports the evidence that the designed devices are of power efficient and high speed. Read-in circuit is also designed and integrated within each of 8 × 8 emitter array elements.

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Asynchronous operation of the live electrooptic imaging technique has been newly proposed and successfully demonstrated, which drastically untightens the severe restrictions regarding synchronization and modulation bandwidth in its conventional master-mode operations. The new operation mode is enabled by generation of an optical LO signal as a frequency-shifted replica of an RF signal to be visualized. Real-time visualizations of free-running MHz-class wide-band FM signals as well as Bluetooth waves carrying multi-Mb/s data emitted from an onboard module have been successfully demonstrated. Limiting factors for the bandwidth thus expanded by a factor of more than 10⁶ have been clarified and systematically evaluated.

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Three dimensional Network-on-chip (3D NoC) is proposed as an effective architecture to optimize system performance. However, thermal issues bring significant challenges on 3D NoC due to high power density. In this paper, we propose a 3D matrix synthesis problem (MSP) based thermal-aware mapping approach under performance constraints for 3D NoC architecture to realize temperature equilibrium and achieve better performance. Genetic algorithm is taken in the approach to obtain the optimal placements. Experimental results show that the proposed approach can achieve a temperature deviation of 45.3% on average compared with the state of art thermal optimization approaches. Moreover, our approach achieves 9.43% power saving and 14.88% delay reduction.

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A Ku-band transceiver chip (TR chip), which can be used for the phased array system, is presented in this paper. It includes a high power amplifier (HPA), a low noise amplifier (LNA) and two switches. The transmitting chain can provide over 2 watt (W) RF output power and 14 dB gain, meanwhile the receiving chain shows less than 3 dB noise figure and 25 dB gain in the frequency range of 15 to 17.5 GHz. A novel switch based on GaAs pHEMT process is also proposed, which can handle over 2 W RF output power without sacrificing the performance of the receiving chain. The size of the TR chip is 3 mm × 3 mm.

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Class-E power amplifiers have found widespread application because of their design simplicity and high-efficiency operation. The nonlinear characteristic of the switching device significantly affects the power amplifier performance, although this is often neglected in theoretical analyses. In this paper, a class-E power amplifier with a shunt capacitance composed of nonlinear and linear capacitance has been mathematically analyzed to obtain the frequency limitation that governs maximum efficiency operation. The analytical method is presented to determine the effective operating frequency for any model of MOSFET device. The practical power amplifier circuit, using a MRF282 MOSFET, was implemented to verify the validity of the theoretical analysis.

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This paper presents a newly energy-efficient switching scheme for successive approximation register (SAR) analog-to-digital converters (ADC). The novel switching method achieves zero power consumption in the first three conversion cycles. The combination of low-power monotonic and charge averaging switching method is utilized for the remaining cycles. Compared to the conventional solution, the proposed switching technique reduces the average switching energy and number of capacitors by 99.18% and 75% respectively. Additionally, the common mode voltage at the comparator input is in a limited variation (less than 1/8Vref).

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A 6.4-THz-spaced 10 × 10 cyclic arrayed waveguide grating (AWG) supporting 64 THz of bandwidth of the T- and O-bands is designed and fabricated. Cyclic operation was realized using only one diffraction order by combining an AWG with double the number of output waveguides and an array of 2 × 1 couplers. The maximum passband peak deviation of the AWG is around 32% of its channel spacing. Such AWG would be useful for coarse T-band applications or for waveband routing in a cascaded AWG configuration.

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Network-on-Chip has become the mainstream interconnection technology for next generation MPSoCs. Exploit of high performance and efficient NoC architecture has been a research hotspot for Network-on-Chip design. In this paper, we present a Dual Priority Congestion Aware Shared-Resource Network-on-Chip architecture (DP-CASR), which could effectively alleviate the resource contention and improve the routing efficiency. Based on 2D-Mesh network, a centralized-distributed hybrid topology is proposed. To make a trade-off between the performance and overheads, both deterministic and adaptive routing metric are introduced in DP-CASR. Compared with typical XY routing and RCA adaptive routing, DP-CASR could achieve higher saturation throughput than that of XY and RCA by 148% and 80% in average, respectively. Moreover, the extra overhead of DP-CASR over 2D Mesh network is only 9%.

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A differential power processing (DPP) isolated-port photovoltaic (PV) architecture based on dual active bridge submodule integrated converters (subMICs) is designed to improve the energy capture efficiency of a PV system in the presence of mismatch conditions. To facilitate the control design, a small-signal model of the DPP PV architecture is developed in this work based on the discrete-time modeling method. Discrete compensator for the subMICs is designed accordingly. The validity of the modeling and control is verified by experimental results.

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A simple transmission line (TL) model is developed for analyzing the electromagnetic pulse (EMP) coupling of a twisted-wire pair (TWP)-TL above a ground plane, illuminated by a external plane wave. To accurately take into account the geometry of the TWP-TL, the TWP-TL is modelled as a cascade of a uniform segment with a different height from the ground plane. Numerical examples are used to illustrate the validity of the proposed TL model for the EMP coupling analysis of TWP-TL.

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In this letter, a novel circuit architecture for active polyphase filter is proposed and analyzed. The currents produced from two source-follower with capacitor and common-source stage in a single-stage are used to realize high-pass and low-pass functions, respectively. Compared to other conventional active polyphase filters, the proposed polyphase filter uses a simpler structure to achieve strong image rejection in a wide band while obtaining lower power consumption, higher operating frequency and smaller chip area. In the 0.18-µm CMOS process, the proposed active polyphase filter occupies less than 0.65 mm² of chip area. From the measurements, the active polyphase filter shows an image rejection ratio of 48.5 dB at frequencies of 5.5 MHz to 26.5 MHz, a voltage gain of 6.8 dB and an IIP3 of 3.8 dBm at 16 MHz while consuming only 3.1 mA from a 1.8-V supply.

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A novel ultra-wideband (UWB) bandpass filter with compact size, improved stopband performance and wider bandwidth is presented in this paper. A new defected microstrip structures resonator (DMSR) is proposed and analyzed theoretically. In order to improve the stopband characteristics, three interdigitated parallel coupled-lines (IPCL) and two complementary split ring resonators (CSRR) are adopted. Finally, a filter prototype is fabricated and measured. The measured results show that the proposed filter achieves a bandwidth of 129% from 2.35 to 10.8 GHz. And the insertion loss is less than 0.5 dB with good return loss.

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This paper presents an adaptive cross approximation (ACA)-based LU decomposition scheme to accelerate direct solution of the characteristic basis function method (CBFM). It takes advantage of the rank-deficient nature of the reduced matrix in CBFM to compress the LU decomposition matrices through the ACA. Therefore, the proposed method can remarkably reduce the memory requirement and accelerate the lower and upper triangular matrices assembly computation as well as matrix-vector multiplication in the solution of the CBFM. Numerical results about the scattering problems are given to demonstrate the accuracy and efficiency of the proposed method.

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Resistive random access memory (ReRAM) has been considered as a promising non-volatile storage technology of next generation especially for embedded application. However, for conventional write scheme with fixed duration and amplitude, power consumption is very high and cell performance degrades due to over-programming. In this paper, we proposed a self-adaptive write driver with fast termination of ramped-up pulse (FT-RPSWD) after write success. The slope detection and feedback mechanism are used to monitor the switching point of cell resistance. The scheme is insensitive to the selection of reference voltage, which is beneficial to ensure write margin even if the resistance variation among cells is severe. The proposed technique is verified on a 256 Kb ReRAM test macro fabricated based on 0.13-µm logic process. The mean value of endurance distribution is improved by 3 orders of magnitude from 10² to 10⁵ and the set and reset energy per bit are reduced significantly.

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