2016 Volume 13 Issue 7 Pages 20160142
Network-on-Chip has become the mainstream interconnection technology for next generation MPSoCs. Exploit of high performance and efficient NoC architecture has been a research hotspot for Network-on-Chip design. In this paper, we present a Dual Priority Congestion Aware Shared-Resource Network-on-Chip architecture (DP-CASR), which could effectively alleviate the resource contention and improve the routing efficiency. Based on 2D-Mesh network, a centralized-distributed hybrid topology is proposed. To make a trade-off between the performance and overheads, both deterministic and adaptive routing metric are introduced in DP-CASR. Compared with typical XY routing and RCA adaptive routing, DP-CASR could achieve higher saturation throughput than that of XY and RCA by 148% and 80% in average, respectively. Moreover, the extra overhead of DP-CASR over 2D Mesh network is only 9%.