IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
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A low-power high-speed true single-phase clock-based divide-by-2/3 prescaler
Wenjian JiangFengqi YuQinjin Huang
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JOURNAL FREE ACCESS

2017 Volume 14 Issue 1 Pages 20160446

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Abstract

A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the TSPC flip-flops is eliminated, and the number of switching stages is reduced to 5. The prescaler is implemented in a standard 0.18-µm CMOS process. It achieves the maximum operating frequency of 5.7 GHz with a measured power consumption of 0.95 mW and 0.98 mW in divide-by-3 mode and divide-by-2 mode, respectively, when operated at 1.5-V power supply.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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