A novel low-power high-speed true single-phase clock-based (TSPC) divide-by-2/3 prescaler is presented. Compared with the conventional topologies, one of the precharge stages in the TSPC flip-flops is eliminated, and the number of switching stages is reduced to 5. The prescaler is implemented in a standard 0.18-µm CMOS process. It achieves the maximum operating frequency of 5.7 GHz with a measured power consumption of 0.95 mW and 0.98 mW in divide-by-3 mode and divide-by-2 mode, respectively, when operated at 1.5-V power supply.

Non-Foster circuits (NFC), in conjunction with the effect of negative impedance, have been applied to design broadband radio frequencies (RF) due to their wideband impedance matching ability. There are many approaches to designing non-Foster circuits that use transistors with loops inside to obtain negative reactance. Hence, conventional NFC has some problems, including complex connectivity and power consumption. In this paper, we analyse other properties of NFC phase and group delay, and we realize that these properties are related to properties of negative group delay (NGD) networks. Therefore, we proposed a new design of passive non-Foster circuits, that is less complicated and does not require power.

This paper presents a GaAs double-balanced mixer (DBM) applying an improved Marchand balun. This structure is achieved by adding a frequency-tuning tail capacitor to the end of the imbalanced coil. By using this tail capacitor, the size of balun is greatly reduced and the IF bandwidth is largely extended. The equivalent circuit modeling and working principle of this structure are described in this paper. The RF bandwidth of the proposed mixer is from 6 GHz to 18 GHz. The measurement result shows that the mixer’s IF bandwidth ranges from DC to 8 GHz with the conversion loss less than 10 dB. Because of the good amplitude and phase performance of the proposed balun, the LO to IF isolation is also improved. The total chip area is 950 × 600 µm².

This letter presents a 2.5 Gb/s half-rate burst-mode clock and data recovery (BMCDR) with enhanced jitter performance. Compared to conventional half-rate BMCDRs, the proposed work uses a single loop gated voltage controlled oscillator (GVCO) to minimize the timing mismatch. And the GVCO has only one gated delay cell to improve jitter performances. In addition, a tri-state phase detector for digital frequency calibration is also proposed in this letter to further reduce jitter caused by the frequency offset between the input data and the GVCO free running clock. The fabricated chip in a 110 nm CMOS technology occupies the area of 0.08 mm². The proposed BMCDR consumes 29 mW with the measured peak to peak jitter of 17.8 ps_p–p (0.022 UI_p–p).

Reliability is an essential issue in circuits design. The methodology of Markova random field (MRF) provides a new way for ultra-low supply voltage design to obtain high noise-immune performance. However, MRF circuits have a lack of the analysis for the supply voltage. In this paper, we use information theory to analyze the low bound of the supply voltage. Then, we prove the MRF circuit has lower supply voltage compared to the traditional circuit under the same output correct probability. The contribution of this paper is providing a mathematical proof for MRF circuit from the information theory viewpoint in low supply voltage design.

This paper described a novel vehicle detection sensor design in which dual microwave Doppler radar transceiver modules were used to detect the movement of a parking vehicle. A motion recognition algorithm was also presented to identify the vehicle behavior and generate the parking space occupancy status. Comparing with existing methods such as magnetometer and optical based detection, the proposed design simplified engineering integration from complex optical system design as well as achieved a high detection accuracy. Experimental results showed that the proposed dual microwave Doppler radar sensor detected the vehicle movement clearly and the parking space occupancy detection accuracy was higher than 98%.

In this letter, a flexible two-section transmission-line transformer with single-band operation is introduced to transform complex source impedance to real load impedance. Two characteristic impedances and their electrical lengths of two-section transmission-lines are derived in closed form. From the newly derived design equations, once the complex source impedance and real load impedance are determined, two characteristic impedances of two-section transmission-lines can be selected arbitrary, then their electrical lengths are calculated automatically. Several simulated examples show that: by using the proposed design equations, there are different group of design parameters for a given condition, the circuit size could be much more compact than those in the previous work, meanwhile, 20 dB bandwidth can be maintained, and harmonic suppression could also be improved. Experimental circuit shows that: circuit size is shrunk to 38.6%, and its harmonic suppression has been improved over 15 dB.

A novel Rectangular waveguide (RWG) filter with integrated transitions is proposed in this letter. The E-plane probe transition, which is employed to couple the energy from the RWG resonator to the microstrip line (MSL), is used as the external coupling mechanism. The integrated design of the filter and transition can reduce the design complexity and size of the circuit. In order to verify the design, a prototype of the filter is fabricated and measured. It provides an in-band return loss and insertion loss of better than 14.6 and 1.5 dB, respectively, in the frequency range of 8.39 to 8.85 GHz.

Convolutional neural network (CNN), a well-known machine learning algorithm, has been widely used in the field of computer vision for its amazing performance in image classification. With the rapid growth of applications based on CNN, various acceleration schemes have been proposed on FPGA, GPU and ASIC. In the implementation of these specific hardware accelerations, the most challenging part is the implementation of 2D convolution. To obtain a more efficient design of 2D convolution in CNN, this paper proposes a novel technique, singular value decomposition approximation (SVDA) to reduce the usage of resources. Experimental results show that the proposed SVDA hardware implementation can achieve a reduction in resources in the range of 14.46% to 37.8%, while the loss of classification accuracy is less than 1%.

This work presents a dual channel 8:1 high voltage (HV) multiplexer (MUX) with a 3-to-8 decoder and 16 HV switches for Battery Management Systems (BMS). Each HV switch consists of two pairs of sub-switches using n- and p-channel drain extended MOS devices with back to back body diode protection, respectively. The two pairs of sub-switches, connected in parallel and with dedicated gate drive signals, allow the HV MUX to have a rail-to-rail output swing and improved sampling accuracy. An experimental prototype is implemented using a 0.35 µm 60 V BCD process. The measurement results reveal that the maximum error of the HV MUX is ±0.2 mV, and the power dissipation is below 2.3 mW with a chip area of only 1.9 × 0.57 mm².

High gain step up DC-DC boost converters are considered as an important part in different renewable energy sources (RES). In this paper a modified high gain setup up DC-DC quadratic boost converter is introduced. The proposed topology not only enhance the high voltage gain but also decrease the voltage stress across the semiconductor switches as well overall converter loses. To validate the proposed method efficacy, experiment performed in laboratory where 5 VDC are given as an input and at output we attained 62.5 volts with output power of 19.5 watts. The maximum efficiency of proposed converter at input power of 20 W is 95.39% and at 3.7 W it is 83.52%. Whereas, the conventional converter efficiency at the same input power is 93.89% and 82.96% respectively.