Area-efficient mixed-radix variable-length FFT processor

Abstract

This paper presents a mixed-radix multipath delay feedback (MDF) FFT processor with variable-length. In order to minimize the number of occupied multipliers while supporting more flexible FFT length, a 4-parallel radix-2³ mixed radix-2/3/4 architecture is adopted. In order to further optimize the area and power consumption, we make efforts in constant multiplier design, twiddle factor generation and butterfly units multiplexing. CSD multiplier is adopted to realize the constant factor multiplication in radix-2³ and radix-3 butterfly. Only one CORDIC, several adders and multipliers are occupied to achieve the 4-parallel twiddle factor generation. A radix-2/3/4 multiplexing butterfly unit with simple control logic is also designed. The design is synthesized with 65 nm CMOS technology. Compared with previous works, the proposed design shows advantages in terms of area, power consumption, and processing latency.