As the main component for modern main memory system, DRAM stores data by capacitors, which must be refreshed periodically to keep the charges. As the size and speed of DRAM devices continue to increase, the overhead of refresh has caused a great power and performance dissipation. In this paper, we proposed a CAM (content-addressable memory)-based Retention-Aware DRAM (CRA-DRAM) system, a hardware implementation that uses CAM and RAM to locate and replace the leaky cells at the IO granularity. Then the entire DRAM is refreshed at a much lower rate. With IO-granularity address of leaky cells stored in CAM at the profiling stage, each access address to CRA-DRAM would be searched to determine where the data are read from or written to. We proved the IO-granularity data replacement technique is completely compatible with the JEDEC standard. The experimental results show that when the refresh period is increased by 6×, CRA-DRAM has a 82.5% refresh reduction, an average DRAM energy reduction of 29.1% and an average system performance improvement of 8.3%. Without modification to memory controller, OS and DRAM devices, CRA-DRAM is quite promising to be applied in DIMM, HBM and HMC.
In order to improve the control efficiency and balance accuracy of rotor automatic balance, a fuzzy self-tuning single neuron PID control method is proposed in this paper. Based on the single neuron PID control method, the fuzzy control theory is introduced to adjust the output gain K of single neuron PID control to realize single neuron PID control with variable step size. In order to verify the superiority of this method, the method we designed in this paper is compared with the traditional PID control method and the single neuron PID control method by the simulation and self-built experimental platform. Experiments and simulation results show that the fuzzy self-tuning single neuron PID control method has faster response time, less overshoot amount and fewer oscillation times than the traditional PID control method and the single neuron PID control method, and has strong robustness and good stability.
We fabricated metal-ferroelectric-metal capacitors and bottom-gate, top-contact nonvolatile ferroelectric transistors (FeFETs) using poly(vinylidene fluoride-trifluoroethylene) [P(VDF-TrFE)] and poly(3-hexylthiophene) (P3HT) on aluminum foil substrates. P(VDF-TrFE) and P3HT layers were formed by the sol-gel method at low temperature. FeFETs on Al foil substrates exhibited similar properties compared with those fabricated on other rigid and flexible substrates.
In this letter, 8-bit paper based printable chipless tag is presented. The tag not only justifies the green electronic concept but also it is examined for sensing functionality. The compact tag structure comprises of seven L-shaped and one I-shaped dipole structure. These conducting tracks/dipole structures are of silver nano-particle based ink having a conductivity of 1.1 × 107 S/m. Each conducting track yields one bit corresponding to one peak. The tag design is optimized and analyzed for three different flexible substrates i.e. paper, Kapton® HN, and PET. The tag has ability to identify 28 = 256 objects, by using different binary combinations. The variation in length of particular conducting strip results in a shift of peak for that specific conducting track. This shift corresponds to logic state-1. The response of the tag for paper, Kapton® HN, and PET substrates is observed in the frequency band of 2.2–6.1 GHz, 2.4–6.3 GHz, and 2.5–6.5 GHz, respectively. The tag has an attractive nature because of its easy printability and usage of low-cost, flexible substrates. The tag can be deployed in various low-cost sensing applications.
This paper presents a mixed-radix multipath delay feedback (MDF) FFT processor with variable-length. In order to minimize the number of occupied multipliers while supporting more flexible FFT length, a 4-parallel radix-23 mixed radix-2/3/4 architecture is adopted. In order to further optimize the area and power consumption, we make efforts in constant multiplier design, twiddle factor generation and butterfly units multiplexing. CSD multiplier is adopted to realize the constant factor multiplication in radix-23 and radix-3 butterfly. Only one CORDIC, several adders and multipliers are occupied to achieve the 4-parallel twiddle factor generation. A radix-2/3/4 multiplexing butterfly unit with simple control logic is also designed. The design is synthesized with 65 nm CMOS technology. Compared with previous works, the proposed design shows advantages in terms of area, power consumption, and processing latency.
A polarization insensitive, compact, fully-passive bit encoding structure exhibiting 1 : 1 resonator-to-bit correspondence is presented. Inspired by frequency selective surface (FSS) based microwave absorbers, the structure readily operates as a chipless radio frequency identification (RFID) tag. The unit cell is composed of several concentric hexagonal loops. Finite repetitions of the unit cell constitute the proposed RFID tag in its entirety. The required bit sequence is encoded in the frequency domain by addition or omission of corresponding nested resonant elements. A functional prototype is fabricated on a commercial-grade grounded FR4 substrate, occupying a physical footprint of 23 × 10 mm2 while offering a capacity of 14 bits. The proposed tag boasts a minuscule profile, and demonstrates polarization insensitivity as well as stable oblique angular performance.
We propose a compact polarization diversity circuit for a silicon waveguide device. It consists of silica waveguides and photonic crystal waveplates, and can convert input light with various polarization states into two output light signals with the same polarization. Setting these circuits at the front and rear of two silicon optical switches, the polarization dependence in the switch can be dramatically suppressed. We fabricated polarization diversity circuits for a 4×4 silicon optical switch and realized a polarization insensitive 4×4 optical switch. The polarization dependent loss was reduced to 1.1 dB and the polarization dependent crosstalk was less than −17 dB.
Many applications compute on sensitive data, such as confidential user information. Even if these applications are terminated, sensitive data often persist in the main memory indefinitely until the deallocated pages are overwritten by OS. The conventional software-only solution of zeroing pages at deallocation generates a significant amount of bursty memory traffic to slow down other processes running concurrently. To address this, we propose Secure DRAM, a novel DRAM architecture that enables low-cost, secure deallocation of physical page frames. By preventing access to unallocated DRAM pages and not refreshing them, Secure DRAM effectively closes the window of vulnerability with minimal performance overhead.
We present a novel bandwidth enhancement technique for a transimpedance amplifier (TIA). The proposed TIA utilizes a common source topology and adopts the current mirror configuration using flipped voltage follower to increase the open-loop gain for the enhanced bandwidth with positive feedback. Circuit simulation results show that the proposed TIA makes it possible to increase the open-loop gain and enlarge the bandwidth by 40% compared with the conventional TIA.
A complete single-poly 2k-bit EEPROM solution including memory cells and peripheral circuits is presented and embedded into a passive RFID tag using a 0.18-µm standard CMOS technology. A charge pump with a Diode-C all-pass network and peripheral circuits without static current are proposed to reduce power consumption. A three-transistor memory cell is adopted for CMOS-compatibility, low operation voltage, and low complexity of drivers. The proposed EERPOM occupies an active area of 0.21 mm2. The leakage current during read operation is 36 nA from 1-V supply, while the static current during write operation is 1.3 µA from 1.8-V supply.
A novel microstrip-fed waveguide filter is proposed in this letter. The H-shaped slots on the back side of the substrate are utilized to connect waveguide cavities and the microstrip circuit. Simultaneously, they are used to realize external coupling of the filter. This design can effectively reduce the size of the circuit and avoid extra transition loss, which is good for system integration. A fifth-order filter at W-band based on H-shaped coupling slots have been fabricated and measured. Good agreements between the simulated and measured results are observed.