A metastability-immune error-resilient flip-flop for near-threshold variation-tolerant designs

Abstract

A metastability-immune error-resilient flip-flop (MIERFF) is proposed to eliminate timing margins. It detects timing errors by generating and capturing a pulse that is wide enough to avoid metastability, in response to the data input transition. Timing errors are immediately corrected by dynamically making the master latch transparent to resample the late-arriving data. The MIERFF improves the system reliability and reduces the correction performance penalty. We apply the MIERFF to a 32-bit embedded processor in a 40 nm CMOS technology. Simulation results show that the proposed design under 0.6 V consumes 47% less energy than the traditional worst case design and achieves 6%–38% energy benefits over previous error detection and correction designs.