In this article we discuss the hardware implementation of a lightweight hash function, named Tav-128 [1], which was purposely designed for constrained devices such as low-cost RFID tags. In the original paper, the authors only provide an estimation of the hardware complexity. Motivated for this, we describe both an ASIC and an FPGA-based implementation of the aforementioned cryptographic primitive, and examine the performance of three architectures optimizing different criteria: area, throughput, and a trade-off between both of them.

Fast switching capability of SiC power devices enables the downsizing of power conversion circuits by high-frequency switching operation. However, high di/dt in fast switching operation for high-frequency switching induces surge voltage. This paper developed low-inductance power module substrate with snubber capacitor directly attached on the substrate to suppress surge voltage in fast switching, and validated the performance of the developed SiC half-bridge power module. The surge voltage was suppressed less than 1/10 of the conventional power module configuration for same switching speed.

With the closed principle of flux-controlled memristors, the parallel, series, and array circuits of flux-controlled memristors are made discussed. The parameters for equivalent flux-controlled memristors of these memristor systems are deduced theoretically. The mathematical relationships between the parameters of equivalent flux-controlled memristors and those of corresponding component memristors are attained. The results are interesting for the application of serie, parallel, and array circuits of flux-controlled memristors.

To realize a highly optical-feedback tolerant distributed feedback laser diode (DFB LD), we investigate a design approach combining transfer-matrixes and rate-equation analyses. As an important design parameter, we use the C coefficient—the coupling strength between the optical field in the laser cavity and the feedback lightwave—and calculate it numerically. On the basis of the results, a novel DFB-LD structure with high tolerance to optical feedback is proposed and the design parameters are optimized.

We propose a phase shift pulse BOTDR (PSP-BOTDR) using probes composed of long and short pulses with phase shift keying modulation, and evaluate its performance by experiment and simulation. Modifying the previous probe configuration reduces signal leakage from the adjacent section to a negligible extent, and achieves truely a spatial resolution of 20 cm.

We have succeeded in the first demonstration of a simple and accurate resonator-superconducting quantum interference device (SQUID) coupling for microwave SQUID multiplexers. A simple theory shows our direct coupling with adjustable fractional inductance in the SQUID loop can decrease the deviation of resonance frequencies from designed values in contrast to a conventional inductive coupling. Our direct coupling provides the individual coupling that can be optimized with keeping identical structure, shape, and dimension of the SQUID among all pixels on the same chip. It covers experimentally three or potentially more factors of a frequency band that is larger than that of cryogenic high electron mobility transistor amplifiers. The deviation of experimental fractional inductance from the designed one is less than −3/+10%.

Multiple clock domains mobile SoCs typically adopt dynamic voltage and frequency scaling (DVFS) for flexible power/energy management. However, adoption of system-level cache under DVFS-enabled CPU may incur abnormal cache hierarchy (i.e., a delay reversal between the high-level and low-level caches). It may lead to performance- and energy-inefficiency due to slower data delivery and meaningless accesses to intermediate levels of caches. To resolve this problem, we propose a DVFS-aware cache bypassing technique. Our technique profiles latencies of the various levels of the caches. Based on the profiled information, our technique adaptively bypasses intermediate levels of caches in the case of abnormal cache hierarchy and applies power-gating to that cache memory for better energy efficiency. According to our evaluation, our technique reduces L2 and system-level cache energy consumption by up to 14.5% while improving performance by up to 0.13% compared to the baseline.

An 8-b single-channel successive approximation register (SAR) analog-to-digital converter (ADC) fabricated in 55 nm CMOS is proposed. With segmented prequantize and bypass digital-to-analog converter (DAC), the unnecessary switching of high weight capacitors are avoided. Two alternating comparators are utilized to reset the comparators completely without the sacrifice of conversion speed. A novel simple and low power background offset calibration technique is implemented. Operating at 325 MS/s, this ADC consumes 6 mW from 1.2 V supply, achieves SNDR of 43.6 dB and SFDR of 59.1 dB with 11-MHz input while occupying 0.011 mm².

Millimeter-wave Holography is a promising technique for security screening to detect concealed weapons. However, a crucial disadvantage of this technique is that the close-range large-aperture operation result in a very short depth of focus. In this paper, a W-band auto-focus holographic imaging system is presented. By calculating and comparing the amplitude integral value of holographic imaging results reconstructed at different focusing distances, the algorithm can assess focusing quality of each imaging result, choose the optimal focusing distance, and extract the optimum viewing image from the imaging results. The scheme of imaging system is described in detail. Both simulation and experimental results are provided to demonstrate that the focusing performance of new auto-focus imaging system is much better than conventional holographic system.

A metastability-immune error-resilient flip-flop (MIERFF) is proposed to eliminate timing margins. It detects timing errors by generating and capturing a pulse that is wide enough to avoid metastability, in response to the data input transition. Timing errors are immediately corrected by dynamically making the master latch transparent to resample the late-arriving data. The MIERFF improves the system reliability and reduces the correction performance penalty. We apply the MIERFF to a 32-bit embedded processor in a 40 nm CMOS technology. Simulation results show that the proposed design under 0.6 V consumes 47% less energy than the traditional worst case design and achieves 6%–38% energy benefits over previous error detection and correction designs.

A decoupling method between two tri-band antennas for WLAN/WiMAX applications is presented. A monopole is first designed with tri-band characteristic; three resonating frequencies are generated by three separate resonators. Then, two tri-band monopoles are employed to develop a MIMO antenna system. The resonators of low band can reduce the mutual coupling for two higher bands by suppressing surface wave propagation. Finally, coupling reduction at low band is achieved by a Ω-shaped metal line to neutralize original coupling. The proposed MIMO antenna covers the 2.4/5.8 GHz WLAN and 3.5 GHz WiMAX bands, with the measured mutual coupling lower than −18 dB.

In this paper, a new compact implementation of S-Box based on composite field arithmetic (CFA) is proposed for block ciphers AES and SM4. Firstly, using CFA technology, the multiplicative inverse (MI) over GF(2⁸) is mapped into GF((2⁴)²) and the new architecture of S-Box is designed. Secondly, the MI over GF(2⁴) is optimized by Genetic algorithm (GA), and the multiplication over GF(2⁴) and the constant matrix multiplications are optimized by delay-aware common sub-expression elimination (DACSE) algorithm. Finally, compared with the direct implementation, the area reduction of MI over GF((2⁴)²) and the new S-Box are up to 49.29% and 43.80%, severally. In 180 nm 1.8 V COMS technology, compared to the synthesized results of AES S-Box and SM4 S-Box, the area and power consumption of the new S-Box are reduced by 24.76% and 38.54%, respectively.

The launch light conditions for the 200-µm core step-index multimode fiber have been defined by the International Electrotechnical Commission. However, we found conditions that give results outside the specified values, even when the launch lights are within the standardized encircled angular flux requirements. We report the transformation of the intensity profile for the fiber core showing non-uniform intensity distributions at practical link lengths. These distributions cause a gap compared to classical geometric models. We verified our proposed approach for a launch light study by using far- and near-field patterns of the fiber.

Sub-threshold circuit is a promising circuit design style for IoT application. This paper concentrated on the delay model based on the transient current model in the sub-threshold region. In order to deduce the path delay model, two ways are adopted, which are the coupling capacitance equivalence and the output waveform equivalence. The distribution of path delays is rigidly proven to be lognormal distribution in the sub-threshold region. Considering different supply voltages, cell driven strengths and load capacitances, the proposed model is also validated by Monte Carlo Spice simulation under SMIC 40 nm CMOS process. Experiments show that proposed model agrees with MC simulation results with error 0.448% under the condition of 0.4 V and 99.7% probability, which proves the feasibility of the model.

Hardware accelerators are being considered as important architectural components in the context of datacenter customization to achieve high performance and low power. Compression has played an important role in computer systems by enhancing storage and communication efficiency in the charge of extra computational cost. In this letter, we present a fully pipelined compression accelerator for the Lempel-Ziv (LZ) compression algorithm. The compression accelerator is verified by using FPGA and fabricated using 65 nm CMOS technology.

Phase-change memories (PCMs) provide the benefits of non-volatility and capacity, but they show low performance, high power consumption, and low endurance for write operations. Such PCM drawbacks are exacerbated in state-of-the-art video processors that code images block-by-block. In this letter, we propose a PCM subsystem that removes unnecessary write operations resulting from the block-by-block accesses of video processors. Experimental results show that our PCM subsystem improves the lifetime and performance of PCMs up to 716 times and 6.8 times, respectively, on average. Moreover, it makes PCMs consume 69.7 times lower power than the conventional PCM subsystem, on average.

The carrier microscopic transport process of uniaxial strained Si n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) has been analyzed under γ-ray radiation. The variation of oxide-trapped charge (N_ot) and interface-trap charge (N_it) with the total dose has also been investigated. A two-dimensional analytical model of threshold voltage (V_th) has been developed with the degradation due to the total dose irradiation taken into consideration. Based on this model, numerical simulation has been carried out by Matlab, and the influence of the total dose, geometry and physics parameters on threshold voltage (V_th) were simulated. In addition, to evaluate the validity of the model, the simulation results were compared with experimental data, and good agreements were confirmed. Thus, the proposed model provides good reference for research on irradiation reliability and application of strained integrated circuit of uniaxial strained Si nanometer n-channel metal-oxide-semiconductor field-effect transistor.

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, based on a novel pre-packing placement for performance optimization. Our results show that after placement and routing LDPack outperforms Xilinx ISE MAP with 8% reduction in area and 5.22% smaller critical path delay, at the cost of 18% more runtime in average.

This paper proposes wideband low-power low-jitter self-biased phase-locked loop (SBPLL) for multi-rate serial link transmitter application. It adopts a proposed low-power source-degeneration voltage-to-current converter not only to save power but also to reduce the phase noise contributed by the voltage-to-current converter. The proposed SBPLL is implemented in a 65-nm CMOS process, and the active core area is 0.01 mm². Measurement result shows that the SBPLL can generate clock with frequency from 1.25 to 6.25 GHz and the loop bandwidth can be kept around 20 MHz regardless of the output frequency. The rms jitter integrated from 10 kHz to 300 MHz is 780 fs at carrier frequency of 6.25 GHz and maximum power efficiency is 0.496 mW/GHz with 1.2-V supply. The figure-of-merit (FOM) is −237.2 dB. The measurement results also show good robustness of the SBPLL over temperature and supply voltage variation.

An energy-efficient, area-efficient, high-accuracy and low-complexity switching scheme for successive approximation register (SAR) analogue-to-digital converter (ADC) is proposed. In the proposed switching scheme, both the first and the second comparisons don’t consume switching energy, and all the rest of comparisons consume little switching energy. As a result, the proposed switching scheme achieves a 95.34% switching energy reduction and a 75% area reduction compared with the conventional method. In addition, only the least significant bit (LSB) is depended on the accuracy of V_cm. Moreover, only two reference voltages are used for each capacitor, which lowers complexity of digital control logic.

In this letter, a direct AC-DC converter for piezoelectric (PE) energy harvesting is proposed, which integrates a Synchronous Switch Harvesting on Inductor (SSHI) circuit, to achieve a resistive impedance matching. An SSHI circuit intends to deal with high impedance of the PE transducer. Then, the converter working in discontinuous conduction mode (DCM), with relative high switching frequency, delivers the harvested energy into the load. The circuit is self-powered and can start even if the storage elements are completely drained. The experimental results show that the proposed circuit has better power extraction capability with a higher output voltage, compared with conventional SSHI rectifier under the same excitation.

Satisfying a demand for higher memory capacity is a major problem for computing systems. Conventional solutions are reaching those limits; instead, DRAM/NVM hybrid main memory systems which consist of emerging Non-Volatile Memory for large capacity and DRAM last-level cache for high access speed were proposed for further improvement. However, in these systems, the two device types share limited memory channels/ranks and NVM channels/ranks are often less utilized than DRAM ones. This paper proposes an OBYST (On hit BYpass to STeal bandwidth) technique to improve memory bandwidth by selectively sending read requests that hit on DRAM cache to NVM instead of busy DRAM. We also propose an inter-device request scheduling policy optimized to OBYST. With negligible area overhead, OBYST improves bandwidth, IPC, and EDP by up to 22%, 21%, and 26% over the baseline without bandwidth optimizations, respectively.

By exploring the mapping schemes with dataflow graph (DFG) transformation and different granularity of task-level parallelism, we presented various AES implementations on a coarse grained reconfigurable architecture (CGRA) to meet the requirements raging from high performance to low power. In comparison with published AES cipher implementations on programable processors, our AES cipher has 14.7∼121.4× higher energy efficiency. Moreover, the design shows the advantage over other CGRAs with 1.3∼4.5× energy efficiency improvement.

As gain, offset, and timing mismatches, nonlinearity mismatches also contribute to spurious components which deteriorate TIADC’s performance. This paper proposes an efficient blind calibration method for nonlinearity mismatches in M-channel TIADCs. A modified model for nonlinearity mismatches is established by exploiting binary Hadamard transform (BHT) and differentiator. The calibration is composed of two stages—mismatches compensation and coefficients identification. The principle of mismatches compensation is to reconstruct estimations of the mismatches-induced spurious components and subtract them from the original TIADC’s output. The coefficients identification is performed based on filtered-x least mean square (FxLMS) algorithm. By using improved model and calibration algorithm, the proposed method consumes less computational resource according to the complexity comparison. To tackle the 4-order nonlinearity mismatches in an 16-channel TIADC, the proposed method consumes 23% fewer multipliers than the previous work. Simulation results reveal that both effective resolution and dynamic range improve a lot after calibration.