IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Layout driven FPGA packing algorithm for performance optimization
Linfeng MoChang WuLei HeGengsheng Chen
著者情報
キーワード: FPGA, packing, placement, layout
ジャーナル フリー

2017 年 14 巻 11 号 p. 20170419

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抄録

FPGA is a 2D array of configurable logic blocks. Packing is to pack logic elements into device specific configurable logic blocks for subsequent placement. The traditional fixed delay model of inter and intra cluster delays used in packing does not represent post-placement delays and often leads to sub-optimal solutions. This paper presents a new layout driven packing algorithm, named LDPack, based on a novel pre-packing placement for performance optimization. Our results show that after placement and routing LDPack outperforms Xilinx ISE MAP with 8% reduction in area and 5.22% smaller critical path delay, at the cost of 18% more runtime in average.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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