IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Low-latency and memory-efficient SDF IFFT processor design for 3GPP LTE
Yeon-Jin KimIn-Gul JangKyung-Ju ChoJin-Gyun Chung
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2017 Volume 14 Issue 12 Pages 20170395

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Abstract

This paper presents a low latency IFFT design method for 3rd generation partnership project long term evolution (3GPP LTE). The proposed method focuses on reducing the delay buffer size in the first stage of single-path delay feedback (SDF) IFFT architectures since the first stage occupies about 50% of the overall delay buffer. In order to reduce the buffer size, we propose the reordering scheme of IFFT input data. By using the reordered input data, both the latency and the memory in the first stage are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 41% compared with conventional architecture.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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