This paper presents a novel single event transient (SET) measurement circuit in SRAM-based field programmable gate arrays (FPGAs). Experimental results demonstrate that the new pulse detector is able to on-chip measure bipolar pulses with a detection limit of near 150 ps, compared with existing pulse detectors, detection capability and detection precision are effectively improved.

Power dissipation is a dominant aspect that limits the performance of microprocessors. In this work adaptive supply and body voltage control is used by applying optimum V_dd and NMOS-PMOS body bias voltages (V_BB-N & V_BB-P) to the microprocessor unit, which compensate the threshold voltage and clock frequency for ultra-low power design. SPICE simulation measurements on a 22-nm technology are used to evaluate the theoretical basics and fundamentals. The results show that, optimal amount of power consumption and temperature reduction have been obtained for different workload and simulation environments.

It is widely known that the inaccuracy of BJT-based CMOS temperature sensors is higher at high temperature range, which greatly limits their application. In this paper, the characteristic of the error after calibration is analyzed. Through the experiments, we discover that the cause of this problem is not circuit related, instead it is process related, which is the mechanical stress generated during manufacturing and packaging. Experimental results show that an accuracy of −0.5∼2 °C can be obtained for the calibrated non-epoxy sensors from −40 °C to 120 °C.

As modern GPUs integrate massive processing elements and limited memories on-chip, the efficiency of using their scratchpad memories becomes important for performance and energy. To meet bandwidth requirement of simultaneously accessing of a thread array, multi-bank design, dividing a scratchpad memory into equally-sized memory modules, are widely used. However, the complex access patterns in real-world applications can cause the bank conflicts which comes from different threads accessing the same bank at the same time, and the conflicts hinder the performance sharply. A mapping function is a method that redistributes the accesses according to access addresses. To reduce bank conflicts some scratchpad memory mapping functions are exploited, such as XOR based hash functions and configurable functions. In this paper, we propose an adaptive mapping function, which can dynamically select a suitable mapping function for applications based on the statistics of first block executing. The experimental results show that 94.8 percent bank conflicts reduced and 1.235× performance improved for 17 benchmarks on GPGPU-sim, a Fermi-like simulator.

This paper presents a low latency IFFT design method for 3rd generation partnership project long term evolution (3GPP LTE). The proposed method focuses on reducing the delay buffer size in the first stage of single-path delay feedback (SDF) IFFT architectures since the first stage occupies about 50% of the overall delay buffer. In order to reduce the buffer size, we propose the reordering scheme of IFFT input data. By using the reordered input data, both the latency and the memory in the first stage are significantly reduced. Simulation results show that the latency for 2048-point IFFT is reduced about 41% compared with conventional architecture.

A micromechanical capacitive accelerometer system is analyzed in this paper, which includes a high-Q sensing element and a high-order switched-capacitor (SC) sigma-delta ΣΔ CMOS interface circuit. The high-Q high-order topology obtained a sub-µg/√Hz noise floor. The loop stability is implemented by the operation of electrostatic feedback force, heavy phase compensation and the off-chip adjusting of distributed-feedback factors. The interface circuit is implemented in a standard 0.5 µm CMOS process. The system consumes 12 mW from a single 5 V supply with the noise level of lower than 400 ng/√Hz. The system bandwidth is 600 Hz and the input range of the accelerometer is ±0.7 g. The measured sensitivity of 2.5 V/g is achieved.

An improved single event upset (SEU) tolerant static random access memory (SRAM) bit-cell with differential read and write capability is proposed. SPICE simulation suggests a more than 1000 times improvement of the critical charge over the standard 6T SRAM cell. With the SEU robustness greatly enhanced at low area and electrical performance costs, the proposed cell is well suited to harsh radiation environment applications such as aerospace and high energy physics.

This paper presents an improved quarter-wave patch antenna assembled in a quad-flat-no-lead (QFN) package for system-in-package (SiP) application. An improved short method is proposed to reduce the size of antenna. Moreover, the influence of the package and the wire-bond has been taken into account in the antenna optimization. It has been found that the length of the bonding wire has an obvious effect on the antenna reflection coefficient. According to the simulation results, a bonding wire length of less than 600 µm is suggested in the antenna assembly. The experimental results show that the proposed antenna operates from 34.3 GHz to 38.8 GHz, and has a gain of 4.1 dBi at 37 GHz. The size of the patch antenna is only 1.1 × 2.0 mm² (0.034λ₀²), and it is very suitable for the wire-bond based SiP application.

In this article, a hybrid model for the current-voltage (I-V) characteristic and its high-order derivatives of III-V FETs is presented. The proposed model divides the entire operating region into several subregions and chooses optimum models in each subregion. The artificial neural network (ANN) techniques are employed to smoothly link the boundaries. The validity of this model has been verified by comparing the measurement and modeled results of a GaAs pHEMT.

An ultra-wideband differential divide-by-1.5 divider based on current-mode logic (CML) is proposed. It consists of a divide-by-3 circuit and an optimized CML-XOR gate. Fully symmetric and differential structure is proposed to extend upper bound working frequency. In the CML-XOR gate, two identical Gilbert cells with optimized eight-input signals are developed to strengthen the pull-down force, which benefits the high-speed division. Fabricated in TSMC 180 nm CMOS process, this divider achieves an operating frequency of 0.3–4.4 GHz for 0 dBm input, and consumes 4.14 mW from 1.8 V supply. The chip size is 0.02 mm².

In this paper, we propose a unified algorithm to concurrently perform multiplication and squaring over GF(2^m) using the bipartite modular multiplication method and deriving common operations. Also we design efficient unified semi-systolic arrays from our proposed algorithm for fast exponentiation. The proposed arrays can be used as a core circuit for various applications. Also our architectures are well suited to VLSI implementation as well.

This paper describes 420 GHz subharmonic mixer based on heterogeneous integrated schottky diode designed by University of Electronic Science and Technology of China (UESTC) and fabricated by China Electronics Technology Group Corporation-13 (CETC-13). The whole circuit including schottky diodes is integrated directly on the 50 µm quartz instead of the traditional 12 um GaAs substrate thus the circuit is much easier to manufacture and the cost is much cheaper. The 3D model of schottky diode is built up in the HFSS to extract the parasitic parameters introduced by the diode package when the operating frequency is extremely high. Source-pull and load-pull methods are used to get the optimum RF, LO and IF embedding impedance in the ADS. Measured results show that the minimum conversion loss is 10 dB at 419 GHz and 422 GHz, SSB conversion loss is less than 14.7 dB from 400 GHz to 440 GHz when the LO power is 5.2 dBm at 210 GHz.

A method for accurate measurement of liquid crystal (LC) dielectric constant at lower terahertz region based on a metamaterial absorber, is proposed. In the proposed method, the permittivities are obtained by fitting the simulated spectral responses to the measurement results of a metamaterial (MM) absorber, in which LC layer acts as a substrate. The proposed method was verified by measurement of dielectric anisotropy of two LC mixtures, and error analysis has shown that the maximum error of the extracted permittivity was less than 1%.

Inductive-coupling wireless connection is a promising interconnect technology for 3D stacked chips packaging. Misalignment between inductors of transmitter chip and receiver chip reduces the mutual inductance, leading to a signal transmit failure. A method to evaluate the signal attenuation caused by inductors misalignment is proposed based on the mutual inductance calculation. Misalignment tolerance under constant circuit parameters is given. Test chips are designed and fabricated in 180 nm CMOS process to verify the method. Measurements of the test chip show that the proposed method match well with testing results.

A two-dimension scanning of phased array antenna has been presented. Aperture coupled microstrip patch antenna (ACMPA) elements are used to form a 2 × 2 array operating at 20 GHz. The array is monolithically fabricated with RF MEMS switches by using surface micromachining and anodic bonding process. The main beam can steer in two dimensions when the phase shifters are on the different state. The measurement results show that the array can complete a beam steering angle of approximate ±30° in both E-plane and H-plane, and the highest gain is 9.5 dB.

This paper presents a flipped voltage follower low dropout regulation with dual-feedback loops (DF-FVF LDR). Compared to other FVF LDRs, the multiple functions of error amplifier in DF-FVF LDR contribute to better regulation capability. The dominant pole is set by a small Miller capacitor leading to stable frequency response. Adaptive bias is further adopted to expand the bandwidth as well. Simulation was performed with 0.35 µm CMOS process and the results show that the gain for the shunt feedback loop is boosted greatly. Load and line regulations are reduced to 5.6 µV/mA and 1.4 mV/V. PSRR is maintained −54 dB at 1 kHz and −24 dB at 100 kHz. When the load current varies between 1 mA and 100 mA within edge time of 1 µs, undershoot and overshoot voltage are 110 mA and 89 mA, and the settling time is only 1.5 µs.

Duty cycle and phase spacing of multi-phase clock are converted to an analog voltage by low-pass filtering a clock pulse and quantized by a low-power analog-to-digital converter (ADC). The pull-up and pull-down strengths and the delay of clock buffer are controlled till the duty cycle and phase spacing measured by the ADC become equal to desired values. A prototype has been implemented in a 28-nm CMOS process for a 12-Gbps serial link transceiver and occupies only 0.0014-mm². Experimental results show the deterministic jitter decreases from 8.12-ps to 0.91-ps by the proposed duty cycle and phase spacing error correction technique. While operating with a 1.0-V supply, the additional power consumed for the duty cycle and phase spacing error correction is only 76-µW.

In video encoder chip, memory interface design is a must to transfer various data between the encoder pipeline and the off-chip memory. Reducing the required off-chip memory bandwidth and improving the memory access efficiency are the two key targets for optimized memory interface design. To achieve these two targets, three novel technologies are proposed in Level C+ coding order based AVS HD video encoder. Firstly, an improved Level C+ coding order with necessary NOP insertions are proposed to achieve 61% bandwidth reduction and make MB pipeline scheduling regular. Secondly, MB-level synchronous memory interface design is proposed by trading off external bandwidth, MB pipeline structure, and internal buffer size. Finally, address mapping and arbitration are proposed to improve the access efficiency by 12%. The optimized memory interface design is successfully implemented on our 1080P@45fps AVS encoder with Xilinx Virtex-6 FPGA at an operating frequency of 200 MHz.

A frequency-scanned antenna is designed to achieve range, azimuth and elevation 3D imaging. The frequency-scanned antenna is the combination of substrate integrated waveguide (SIW) slot array and planar array antenna. Angle and range information can be obtained using a single frequency-scanned antenna. So the azimuth and elevation information can be obtained respectively with two orthogonal frequency-scanned antennas in the horizontal and vertical direction. Based on the captured range, azimuth and elevation information, a 3D scenario can be constructed. The frequency-scanned antennas working in the range of 24 to 25.6 GHz have been fabricated, and imaging experiments on different scenarios have been carried out.

This paper proposes an energy-efficient, 12-stage charge pump with constant threshold voltage. This new charge pump utilizes 2 pairs of non-overlapping clocks. Under control of an extra pair of clocks, each charge pump cell (CPC) is equivalent to a switch. Without reduction by a threshold voltage and the limitation of body effects, a higher output voltage than that of the traditional charge pump is obtained by the proposed circuit, which is fabricated in a 0.18 µm complementary metal-oxide semiconductor (CMOS) process. With an input voltage from 0.7 V to 1.4 V, the output voltage range is from 5.8 V to 12.5 V. With a 2-pF load capacitor, the power consumption is only 62.7 µW at maximum DC output voltage of 12.5 V. This circuit is intended to generate an on-chip bias voltage for a microelectromechanical systems (MEMS) microphone.

A simple bowtie-shaped MIMO dielectric resonator antenna (DRA) resonating at 2.45 GHz with 75 MHz measured common bandwidth for both ports is presented in this paper for 2.40–2.48 GHz WIFI band applications. The MIMO characteristics are obtained by simultaneously exciting the TE_δ21 modes by coaxial probe and TM_22δ modes by coupled aperture feed in the DRA. Omni-directional radiation patterns are obtained in both principle planes, simulated and measured radiation patterns are found to be close to each other. Moreover, the proposed bowtie-shaped DRA is compact, exhibits high isolation (25 dB) and relatively low correlation (0.0156) suggesting its suitability for the MIMO applications.

This work presents a low power dual-mode electrocardiogram (ECG) processor with QRS detection and ECG signal lossless compression. An adaptive difference-insensitive filter is proposed to eliminate redundant information in signal for QRS detection, which helps minimize calculation power. It is also adopted as a noise estimator and used to improve the noise tolerance of the detector. Furthermore, in compression mode, linear predictor with a novel adaptive length encoder is applied to the ECG data lossless compression, achieving a compression ratio (CR) of 2.42 with 1.06 K gate count. Implemented in 40 nm CMOS technology, the processor has a total core area of 6806 µm², with 36 nW power consumption in detection mode and 7.3 nW in compression mode under a supply voltage of 0.5 V.