IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
0.3–4.4 GHz wideband CMOS frequency divide-by-1.5 with optimized CML-XOR gate
Hua ChenGuiliang GuoQiangtao LaiYulin ZhangJingyu HanYuepeng Yan
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JOURNALS FREE ACCESS

2017 Volume 14 Issue 12 Pages 20170450

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Abstract

An ultra-wideband differential divide-by-1.5 divider based on current-mode logic (CML) is proposed. It consists of a divide-by-3 circuit and an optimized CML-XOR gate. Fully symmetric and differential structure is proposed to extend upper bound working frequency. In the CML-XOR gate, two identical Gilbert cells with optimized eight-input signals are developed to strengthen the pull-down force, which benefits the high-speed division. Fabricated in TSMC 180 nm CMOS process, this divider achieves an operating frequency of 0.3–4.4 GHz for 0 dBm input, and consumes 4.14 mW from 1.8 V supply. The chip size is 0.02 mm2.

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© 2017 by The Institute of Electronics, Information and Communication Engineers
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